# US 9,040,408 B1 · Techniques for wafer-level processing of QFN packages

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- Number: US 9,040,408 B1
- Document ID: US9040408B1
- Status: Granted
- Kind: B1
- Application number: 14/134,171
- Filed: 2013-12-19
- Granted: 2015-05-26
- Earliest claimed: 2013-03-13
- Assignees: Maxim Integrated Products, Inc.
- Applicants: Maxim Integrated Products, Inc.
- Inventors: Tiao Zhou; Joseph W. Serpiello; Md. Kaysar Rahim; Yong L. Xu; Karthik Thambidurai; Viren Khandekar
- Web page: https://patentgrep.com/patent/US9040408B1

## CPC

- H10W 74/137: {the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence)}
- H10W 74/114: {by a substrate and the encapsulations}
- H10W 90/00: Package configurations
- H10W 99/00: Subject matter not provided for in other groups of this subclass
- H10W 72/01233: {in liquid form, e.g. spin coating, spray coating or immersion coating}
- H10W 72/019: {of bond pads}
- H10W 72/01935: {by plating, e.g. electroless plating or electroplating}
- H10W 72/01955: {by using masks}
- H10W 72/0198: {batch processes}
- H10W 72/07252: {changes in structures or sizes}
- H10W 72/221: {Structures or relative sizes}
- H10W 72/227: {Multiple bumps having different sizes}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/242: {relative to the surface, e.g. recessed, protruding}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/921: {Structures or relative sizes of bond pads}
- H10W 72/922: {Bond pads being integral with underlying chip-level interconnections}
- H10W 72/9223: {with redistribution layers [RDL]}
- H10W 72/9226: {with via interconnections}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/926: {Multiple bond pads having different sizes}
- H10W 72/9413: {on encapsulations}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/944: {Dispositions of multiple bond pads}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/957: {Multiple bond pads having different materials}
- H10W 90/28: the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape
- H10W 90/722: {between stacked chips}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Semiconductor package devices, such as wafer-level package semiconductor devices, are described that have pillars for providing electrical interconnectivity. In an implementation, the wafer-level package devices include an integrated circuit chip having at least one pillar formed over the integrated circuit chip. The pillar is configured to provide electrical interconnectivity with the integrated circuit chip. The wafer-level package device also includes an encapsulation structure configured to support the pillar.

## Claims

### Claim 1

A process comprising:
forming at least one pillar over a semiconductor wafer;
forming an encapsulation structure over the semiconductor wafer, the encapsulation structure at least substantially encapsulating the at least one pillar;
etching the encapsulation structure to remove an outer section of the encapsulation structure so that a portion of the at least one pillar extends beyond the encapsulation structure; and
applying a solder layer to the at least one pillar, the solder layer extending over at least part of a sidewall of the portion of the at least one pillar that extends beyond the encapsulation structure.

### Claim 2 (depends on 1)

The process as recited in claim 1, wherein the etching of the encapsulation structure comprises using a dry etch process to etch the encapsulation structure.

### Claim 3 (depends on 2)

The process as recited in claim 2, wherein the dry etch process comprises a plasma etch process.

### Claim 4 (depends on 1)

The process as recited in claim 1, wherein the etching of the encapsulation structure comprises using a wet etch process to etch the encapsulation structure.

### Claim 5 (depends on 1)

The process as recited in claim 1, wherein forming at least one pillar further comprises:
applying a first photoresist layer over the semiconductor wafer;
patterning and at least partially etching the first photoresist layer to form a first etched area;
depositing conductive material in the first etched area;
applying a second photoresist layer over the first photoresist layer;
patterning and at least partially etching the second photoresist layer to form a second etched area, the second etched area formed over the first etched area;
depositing conductive material in the second etched area to form the at least one pillar; and
at least substantially removing the first photoresist layer and the second photoresist layer.

### Claim 6 (depends on 1)

The process as recited in claim 1, wherein forming an encapsulation structure further comprises depositing an epoxy material over the semiconductor wafer, the encapsulation structure at least partially encapsulating the at least one pillar.

### Claim 7 (depends on 1)

The process as recited in claim 1, wherein the at least one pillar comprises a copper pillar.

### Claim 8

A wafer-level package device comprising:
an integrated circuit die having a surface;
an encapsulation structure disposed over the surface;
at least one pillar extending from the surface through the encapsulation structure, the at least one pillar having an end distal from the surface including a portion that extends beyond the encapsulation structure, the at least one pillar configured to provide an electrical interconnection to the integrated circuit die; and
a solder layer disposed over the end of the at least one pillar, the solder layer extending from the encapsulation structure over a vertical sidewall of the portion of the at least one pillar that extends beyond the encapsulation structure.

### Claim 9 (depends on 8)

The wafer-level package device as recited in claim 8, wherein the at least pillar comprises a copper pillar.

### Claim 10 (depends on 8)

The wafer-level package device as recited in claim 8, wherein the encapsulation structure comprises an epoxy material.

### Claim 11 (depends on 8)

The wafer-level package device as recited in claim 8, wherein the at least one pillar comprises a plurality of pillars extending from the surface of the integrated circuit die.

### Claim 12

A process comprising:
forming at least one pillar over a semiconductor wafer;
forming an encapsulation structure over the semiconductor wafer, the encapsulation structure at least substantially encapsulating the at least one pillar;
applying under bump metallization (UBM) over the at least one pillar; and
applying a solder layer to the under bump metallization (UBM), the solder layer extending from the encapsulation structure over a vertical sidewall of the under bump metallization (UBM).

### Claim 13 (depends on 12)

The process as recited in claim 12, wherein the application of the under bump metallization (UBM) comprises:
applying a mask over an outer surface of the encapsulation structure, the mask exposing an outer surface of the at least one pillar;
applying the under bump metallization (UBM) over the outer surface of the at least one pillar; and
removing the mask.

### Claim 14 (depends on 12)

The process as recited in claim 12, further comprising forming a redistribution layer (RDL) over the encapsulation structure, the redistribution layer (RDL) electrically connecting the at least one pillar and the under bump metallization (UBM).

### Claim 15 (depends on 14)

The process as recited in claim 14, wherein the forming of the redistribution layer (RDL) and the applying of the under bump metallization comprises:
applying a first mask over an outer surface of the encapsulation structure, the first mask exposing an outer surface of the at least one pillar and patterned to form the redistribution layer (RDL);
applying the redistribution layer (RDL);
applying a second mask over the first mask and the redistribution layer (RDL), the second mask exposing at least a portion of the redistribution layer (RDL) and patterned to form the under bump metallization (UBM);
applying the under bump metallization (UBM); and
removing the first mask and the second mask.

### Claim 16 (depends on 12)

The process as recited in claim 12, wherein forming at least one pillar further comprises:
applying a first photoresist layer over the semiconductor wafer;
patterning and at least partially etching the first photoresist layer to form a first etched area;
depositing conductive material in the first etched area;
applying a second photoresist layer over the first photoresist layer;
patterning and at least partially etching the second photoresist layer to form a second etched area, the second etched area formed over the first etched area;
depositing conductive material in the second etched area to form the at least one pillar; and
at least substantially removing the first photoresist layer and the second photoresist layer.

### Claim 17 (depends on 12)

The process as recited in claim 12, wherein forming an encapsulation structure further comprises depositing an epoxy material over the semiconductor wafer, the encapsulation structure at least partially encapsulating the at least one pillar.

### Claim 18 (depends on 12)

The process as recited in claim 12, wherein the at least one pillar comprises a copper pillar.

### Claim 19

A wafer-level package device comprising:
an integrated circuit die having a surface;
at least one pillar extending from the surface, the at least one pillar having an end distal from the surface, the at least one pillar configured to provide an electrical interconnection to the integrated circuit die;
an encapsulation structure disposed over the surface, the encapsulation structure at least partially enclosing the at least one pillar;
under bump metallization (UBM) disposed over the at least one pillar and encapsulation structure; and
a solder layer disposed over the end of the at least one pillar, the solder layer extending from the encapsulation structure over a vertical sidewall of the under bump metallization (UBM).

### Claim 20 (depends on 19)

The wafer-level package device as recited in claim 19, wherein the at least pillar comprises a copper pillar.

### Claim 21 (depends on 19)

The wafer-level package device as recited in claim 19, wherein the encapsulation structure comprises an epoxy material.

### Claim 22 (depends on 19)

The wafer-level package device as recited in claim 19, further comprising a redistribution layer (RDL) disposed over the encapsulation structure and at least one pillar, the redistribution layer (RDL) electrically connecting the at least one pillar and the under bump metallization (UBM).