# US 9,040,406 B2 · Semiconductor chip with power gating through silicon vias

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- Number: US 9,040,406 B2
- Document ID: US9040406B2
- Status: Granted
- Kind: B2
- Application number: 13/803,895
- Filed: 2013-03-14
- Published: 2014-09-18
- Granted: 2015-05-26
- Earliest claimed: 2013-03-14
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Karl R. Erickson; Phil C. Paone; David P. Paulsen; John E. Sheets, II; Gregory J. Uhlmann; Kelly L. Williams
- Web page: https://patentgrep.com/patent/US9040406B2

## CPC

- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10P 74/273: {Interconnections for measuring or testing, e.g. probe pads}
- H10W 20/021: {of interconnections within wafers or substrates}
- H10W 20/0245: {comprising use of blind vias during the manufacture}
- H10W 20/0265: {characterised by the sidewall insulation}
- H10W 20/421: {Skip vias, i.e. vias that do not connect all metallization layers that they pass through}
- H10W 20/427: {Power or ground buses}
- H10W 20/491: {Antifuses, i.e. interconnections changeable from non-conductive to conductive}
- H10B 20/25: One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links
- H10W 20/42: Vias, e.g. via plugs
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A semiconductor chip includes a substrate having a frontside and a backside coupled to a ground. The chip includes a circuit in the substrate at the frontside. A through silicon via (TSV) having a front-end, a back-end, and a lateral surface is included. The back-end and lateral surface of the TSV are in the substrate, and the front-end of the TSV is substantially parallel to the frontside of the substrate. The chip also includes an antifuse material deposited between the back-end and lateral surface of the TSV and the substrate. The antifuse material insulates the TSV from the substrate. The chip includes a ground layer insulated from the substrate and coupled with the TSV and the circuit. The ground layer conducts a program voltage to the TSV to cause a portion of the antifuse material to migrate away from the TSV, thereby connecting the circuit to the ground.

## Claims

### Claim 1

A method of manufacturing a semiconductor chip, the method comprising:
providing a semiconductor substrate having a frontside surface and a backside surface, the backside surface being coupled to a ground;
forming a functional circuit in the semiconductor substrate at the frontside surface, the functional circuit electrically isolated from the semiconductor substrate;
forming a through silicon via (TSV) having a front-end surface, a back-end surface, and a lateral surface, the back-end surface and lateral surface of the TSV being in the semiconductor substrate, and the front-end surface of the TSV being substantially parallel to the frontside surface of the semiconductor substrate;
depositing an antifuse material between the back-end and lateral surfaces of the TSV and the semiconductor substrate, the antifuse material being configured to insulate the TSV from the semiconductor substrate; and
forming a functional ground layer insulated from the semiconductor substrate and electrically coupled with the TSV and the functional circuit, wherein the functional ground layer is configured to conduct a program voltage to the TSV to cause a portion of the antifuse material to migrate away from the TSV, thereby electrically connecting the functional circuit to the ground.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
forming a power supply layer configured to supply a supply voltage to the functional circuit.

### Claim 3 (depends on 1)

The method of claim 1, further comprising:
electrically coupling a solder bump with the functional ground layer, wherein the solder bump is configured to receive one of a test voltage and the program voltage, the test voltage to test the functional circuit.

### Claim 4 (depends on 1)

The method of claim 1, wherein the semiconductor substrate is a bulk semiconductor substrate.

### Claim 5 (depends on 1)

The method of claim 1, wherein the semiconductor substrate is adequately doped to electrically couple the TSV to ground when the antifuse material is blown.

### Claim 6 (depends on 1)

The method of claim 1, wherein a conducting area formed by blowing the antifuse material between the TSV and the semiconductor substrate improves with use of semiconductor chip.

### Claim 7 (depends on 1)

The method of claim 1, further comprising forming two or more power islands, wherein a first power island includes the functional circuit and the TSV.

### Claim 8

A method of power gating a semiconductor chip, the method comprising:
providing a semiconductor chip, the semiconductor chip including:
a semiconductor substrate having a frontside surface and a backside surface, the backside surface being coupled to a ground,
a functional circuit in the semiconductor substrate at the frontside surface, the functional circuit electrically isolated from the semiconductor substrate,
a through silicon via (TSV) having a front-end surface, a back-end surface, and a lateral surface, the back-end surface and lateral surface of the TSV being in the semiconductor substrate, and the front-end surface of the TSV being substantially parallel to the frontside surface of the semiconductor substrate,
an antifuse material deposited between the back-end and lateral surfaces of the TSV and the semiconductor substrate, the antifuse material being configured to insulate the TSV from the semiconductor substrate, and
a functional ground layer insulated from the semiconductor substrate and electrically coupled with the TSV, and the functional circuit, wherein the functional ground layer is configured to conduct a program voltage to the TSV to cause a portion of the antifuse material to migrate away from the TSV, thereby electrically connecting the functional circuit to the ground;
determining whether the functional circuit is functional; and
if the functional circuit is functional, blowing the antifuse material with a program voltage to ground the functional circuit to the substrate ground.

### Claim 9 (depends on 8)

The method of claim 8, wherein the semiconductor chip includes a power supply layer configured to supply a supply voltage to the functional circuit.

### Claim 10 (depends on 9)

The method of claim 9, wherein blowing the antifuse material includes raising the supply voltage and the program voltage together so as not to exceed a maximum voltage differential across the functional circuit and providing a high enough program voltage to blow the antifuse material.

### Claim 11 (depends on 8)

The method of claim 8, wherein determining whether the functional circuit is functional and blowing the antifuse material is done by applying a respective test voltage and a respective program voltage to a solder bump electrically coupled with the functional ground layer.

### Claim 12 (depends on 8)

The method of claim 8, wherein the semiconductor substrate is adequately doped to electrically couple the TSV to ground when the antifuse material is blown.

### Claim 13 (depends on 8)

The method of claim 8, wherein the semiconductor chip includes two or more power islands, wherein a first power island includes the functional circuit and the TSV.