# US 9,040,404 B2 · Replacement metal gate structure for CMOS device

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- Number: US 9,040,404 B2
- Document ID: US9040404B2
- Status: Granted
- Kind: B2
- Application number: 13/676,483
- Filed: 2012-11-14
- Published: 2014-05-15
- Granted: 2015-05-26
- Earliest claimed: 2012-11-14
- Assignees: International Business Machines Corporation; Globalfoundries Inc.
- Applicants: International Business Machines Corporation; GLOBAL FOUNDRIES Inc
- Inventors: Takashi Ando; Kisik Choi; Srikanth B. Samavedam
- Web page: https://patentgrep.com/patent/US9040404B2

## CPC

- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 84/0177: {the gate conductors having different materials or different implants}
- H10D 84/0181: {Manufacturing their gate insulating layers}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83135: {the IGFETs characterised by having different gate conductor materials or different gate conductor implants}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method of fabricating a replacement metal gate structure for a CMOS device. The method includes forming a dummy gate structure on an nFET portion and a pFET portion of the CMOS device; depositing an interlayer dielectric between the dummy gate structures; removing the dummy gate structures from the nFET portion and the pFET portion, resulting in a recess on the nFET portion and a recess on the pFET portion; depositing a first layer of titanium nitride into the recesses on the nFET portion and pFET portion; removing the first layer of titanium nitride from the nFET portion only; depositing a second layer of titanium nitride into the recesses on the nFET portion and pFET portion; depositing a gate metal onto the second layer of titanium nitride in the recesses on the nFET portion and pFET portion to fill the remainder of the recesses.

## Claims

### Claim 1

A method of fabricating a replacement metal gate structure for a CMOS device on a semiconductor substrate comprising:
forming a high dielectric constant (high-k) dielectric on an nFET portion of the CMOS device and on a pFET portion of the CMOS device;
forming a dummy gate structure on the high-k dielectric of the nFET portion of the CMOS device and on the high-k dielectric of the pFET portion of the CMOS device, each of the dummy gate structures comprising a layer of nitride, a layer of polysilicon or amorphous silicon and a nitride hard mask;
forming spacers on the dummy gate structures;
depositing an interlayer dielectric between the dummy gate structures;
removing the dummy gate structures from the nFET portion and the pFET portion, resulting in a recess bounded by the spacers on the nFET portion and a recess bounded by the spacers on the pFET portion, the recesses having high-k dielectric only on a bottom of each of the recesses;
depositing a first layer of titanium nitride into the recesses in contact with the high-k dielectric on the nFET portion and pFET portion, the first layer of titanium nitride being present only the high-k dielectric in the nFET portion and pFET portion;
removing the first layer of titanium nitride from the nFET portion only to expose the high-k dielectric;
depositing a second layer of titanium nitride into the recesses on the nFET portion and pFET portion, the second layer of titanium nitride being in direct contact with the high-k dielectric in the nFET portion and in direct contact with the first layer of titanium nitride in the pFET portion;
depositing titanium aluminum onto the second layer of titanium nitride in the recesses on the nFET portion and pFET portion; and
filling the remainder of the cavity on the nFET portion and pFET portion with a metal different from titanium aluminum.

### Claim 2 (depends on 1)

The method of claim 1 wherein the second layer of titanium nitride is titanium-rich such that the second layer of titanium nitride is greater than 50 atomic percent titanium.

### Claim 3 (depends on 1)

The method of claim 1 wherein after depositing a first layer of titanium nitride further comprising oxidizing the first layer of titanium nitride at a temperature of 400° C. for 1 to 10 minutes.

### Claim 4 (depends on 1)

The method of claim 1 wherein after depositing a second layer of titanium nitride further comprising oxidizing the second layer of titanium nitride at a temperature of 400° C. for 1 to 10 minutes.

### Claim 5 (depends on 1)

The method of claim 1 wherein the metal different from titanium aluminum comprises aluminum or tungsten.