# US 9,040,398 B2 · Method of fabricating seminconductor devices including self aligned refractory contacts

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 9,040,398 B2
- Document ID: US9040398B2
- Status: Granted
- Kind: B2
- Application number: 11/434,853
- Filed: 2006-05-16
- Published: 2007-11-22
- Granted: 2015-05-26
- Earliest claimed: 2006-05-16
- Assignees: Cree, Inc.
- Applicants: Adam William Saxler; Scott Sheppard
- Inventors: Adam William Saxler; Scott Sheppard
- Web page: https://patentgrep.com/patent/US9040398B2

## CPC

- H10D 30/4755: {having wide bandgap charge-carrier supplying layers, e.g. modulation doped HEMTs such as n-AlGaAs/GaAs HEMTs}
- H10D 30/015: {of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT}
- H10P 95/904: {of Group III-V semiconductors}
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Methods of forming semiconductor devices are provided by forming a semiconductor layer on a semiconductor substrate. A mask is formed on the semiconductor layer. Ions having a first conductivity type are implanted into the semiconductor layer according to the mask to form implanted regions on the semiconductor layer. Metal layers are formed on the implanted regions according to the mask. The implanted regions and the metal layers are annealed in a single step to respectively activate the implanted ions in the implanted regions and provide ohmic contacts on the implanted regions. Related devices are also provided.

## Claims

### Claim 1

A method of forming a semiconductor device, the method comprising:
providing a semiconductor layer;
forming a mask on the semiconductor layer;
implanting ions having a first conductivity type into the semiconductor layer according to the mask to form implanted regions on the semiconductor layer;
forming metal layers on the implanted regions according to the mask; and
annealing the implanted regions and the metal layers in a single step to respectively activate the implanted ions in the implanted regions and provide ohmic contacts on the implanted regions,
wherein the semiconductor device comprises a Group III-nitride semiconductor device.

### Claim 2 (depends on 1)

The method of claim 1:
wherein providing the semiconductor layer comprises:
forming a channel layer on the semiconductor substrate;
forming a barrier layer on the channel layer; and
forming a protective layer on the barrier layer; and
wherein forming the mask comprises forming the mask on the protective layer.

### Claim 3 (depends on 2)

The method of claim 2:
wherein implanting ions is preceded by etching the protective layer according to the mask to expose at least a portion of a surface of the barrier layer; and
wherein implanting ions further comprising implanting ions having the first conductivity type into the barrier layer according to the mask to form implanted regions on the barrier layer.

### Claim 4 (depends on 3)

The method of claim 3, wherein the implanted regions extend at least partially into the channel layer.

### Claim 5 (depends on 2)

The method of claim 2, wherein implanting ions comprises implanting ions having the first conductivity type into the protective layer and the barrier layer according to the mask to form implanted regions in the protective layer and the barrier layer, the method further comprising:
etching the protective layer according to the mask to expose at least a portion of the implanted regions of the barrier layer.

### Claim 6 (depends on 5)

The method of claim 5, wherein the implanted regions extend at least partially into the channel layer.

### Claim 7 (depends on 2)

The method of claim 2, wherein the protective layer comprises a high purity nitrogen (HPN) layer.

### Claim 8 (depends on 7)

The method of claim 7, wherein the HPN layer has a thickness of from about 50 to about 150 nm.

### Claim 9 (depends on 7)

The method of claim 7, wherein the HPN layer comprises a layer of HPN having a thickness of from about 50 to about 150 nm and a silicon dioxide (SiO2) layer on the HPN layer having a thickness of from about 100 to about 250 nm.

### Claim 10 (depends on 1)

The method of claim 1, wherein the ohmic contacts include at least one refractory metal.

### Claim 11 (depends on 10)

The method of claim 10, wherein the refractory metal includes Ti, TiW, Mo, Ta, W, WSi, Re, Nb, TiWN, NiSi and/or TiSi.

### Claim 12 (depends on 1)

The method of claim 1, wherein the ohmic contacts are self-aligned to the implanted regions.

### Claim 13 (depends on 1)

The method of claim 1, wherein the first conductivity type comprises an n-type conductivity.

### Claim 14 (depends on 13)

The method of claim 13, wherein implanting ions comprising implanting silicon ions.

### Claim 15 (depends on 1)

The method of claim 1, wherein annealing comprises annealing the implanted regions and the metal layer at a temperature of at least about 950° C.

### Claim 16

A method of forming a Group III-nitride semiconductor device, the method comprising:
providing a semiconductor layer;
selectively implanting ions into the semiconductor layer to provide highly doped implanted regions in the semiconductor layer;
forming a refractory metal layer on the highly doped implanted regions in the semiconductor layer, wherein the highly doped implanted regions and refractory metal layer are both formed using a single mask; and
annealing the highly doped implanted regions and the refractory metal layer in a single step to respectively activate the implanted ions of the highly doped implanted regions and form ohmic contacts that are self-aligned to the implanted regions on the implanted regions,
wherein providing the semiconductor layer comprises:
forming a channel layer on the semiconductor substrate;
forming a barrier layer on the channel layer; and
forming a protective layer on the barrier layer.

### Claim 17 (depends on 16)

The method of claim 16, further comprising forming a mask on the protective layer, wherein selectively implanting comprises selectively implanting ions into the semiconductor layer according to the mask and wherein forming a refractory metal layer further comprises forming a refractory metal layer on the highly doped implanted regions in the semiconductor layer according to the mask.

### Claim 18 (depends on 17)

The method of claim 17:
wherein selectively implanting ions is preceded by etching the protective layer according to the mask to expose at least a portion of a surface of the barrier layer; and
wherein selectively implanting ions further comprises selectively implanting ions having the first conductivity type into the barrier layer according to the mask to form implanted regions on the barrier layer.

### Claim 19 (depends on 18)

The method of claim 18, wherein the implanted regions extend at least partially into the channel layer.

### Claim 20 (depends on 17)

The method of claim 17, wherein selectively implanting ions comprises selectively implanting ions having the first conductivity type into the protective layer and the barrier layer according to the mask to form implanted regions in the protective layer and the barrier layer, the method further comprising:
etching the protective layer according to the mask to expose at least a portion of the implanted regions of the barrier layer.

### Claim 21 (depends on 20)

The method of claim 20, wherein the implanted regions extend at least partially into the channel layer.

### Claim 22 (depends on 16)

The method of claim 16, wherein the protective layer comprises a high purity nitrogen (HPN) layer.

### Claim 23 (depends on 22)

The method of claim 22, wherein the HPN layer has a thickness of from about 50 to about 150 nm.

### Claim 24 (depends on 22)

The method of claim 22, wherein the HPN layer comprises a layer of HPN having a thickness of from about 50 to about 150 nm and a silicon dioxide (SiO2) layer on the HPN layer having a thickness of from about 100 to about 250 nm.

### Claim 25 (depends on 16)

The method of claim 16, wherein the refractory metal includes Ti, TiW, Mo, Ta, W, WSi, Re, Nb, TiWN, NiSi and/or TiSi.

### Claim 26 (depends on 16)

The method of claim 16, wherein the implanted ions comprise n-type conductivity ions.

### Claim 27 (depends on 26)

The method of claim 26, wherein the n-type conductivity ions comprise silicon ions.

### Claim 28 (depends on 16)

The method of claim 16, wherein annealing comprises annealing the implanted regions and the refractory metal layer at a temperature of at least about 950° C.

### Claim 29 (depends on 1)

The method of claim 1:
wherein providing the semiconductor layer comprises forming a protective layer; and
wherein implanting the ions is preceded by etching the protective layer according to the mask.

### Claim 30

A method of forming a semiconductor device, the method comprising:
providing a semiconductor layer;
providing a protective layer on the semiconductor layer;
providing a single mask on the protective layer;
etching the protective layer according to the mask;
implanting ions having a first conductivity type into the semiconductor layer according to the mask to form implanted regions on the semiconductor layer; and
providing metal layers on the implanted regions according to the mask.

### Claim 31 (depends on 30)

The method of claim 30, further comprising annealing the implanted regions and the metal layers in a single step to respectively activate the implanted ions in the implanted regions and provide ohmic contacts on the implanted regions.

### Claim 32 (depends on 1)

The method of claim 1, wherein the semiconductor device is a gallium nitride (GaN) semiconductor device.

### Claim 33 (depends on 32)

The method of claim 32, wherein the GaN semiconductor device comprises a High Electron Mobility Transistor (HEMT).