# US 9,040,394 B2 · Method for fabricating a semiconductor device

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- Number: US 9,040,394 B2
- Document ID: US9040394B2
- Status: Granted
- Kind: B2
- Application number: 13/795,701
- Filed: 2013-03-12
- Published: 2014-09-18
- Granted: 2015-05-26
- Earliest claimed: 2013-03-12
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Jin-Bum Kim
- Web page: https://patentgrep.com/patent/US9040394B2

## CPC

- H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D 30/0275: {forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised source or drain regions}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D 64/015: {removing at least parts of gate spacers, e.g. disposable spacers}
- H10D 84/0128: {Manufacturing their channels}
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method for fabricating a semiconductor device includes forming a plurality of gate patterns including a top portion and a bottom portion on a substrate, forming a sacrificial layer contacting the bottom portions of the gate patterns, forming a first spacer on lateral surfaces of the top portions of the gate patterns after forming the sacrificial layer, removing the sacrificial layer after forming the first spacer, and forming a plurality of first recesses on lateral surfaces of the gate patterns after removing the sacrificial layer.

## Claims

### Claim 1

A method for fabricating a semiconductor device, the method comprising:
forming a plurality of gate patterns including a top portion and a bottom portion on a substrate;
forming a sacrificial layer contacting the bottom portions of the gate patterns;
forming a first spacer on lateral surfaces of the top portions of the gate patterns after forming the sacrificial layer;
removing the sacrificial layer from under the first spacer after forming the first spacer; and
forming a plurality of first recesses at the side of the gate patterns after removing the sacrificial layer.

### Claim 2 (depends on 1)

The method of claim 1, wherein the first spacer entirely overlaps the first recesses.

### Claim 3 (depends on 1)

The method of claim 1, wherein the forming of the sacrificial layer comprises: forming the sacrificial layer using directional deposition.

### Claim 4 (depends on 3)

The method of claim 3, wherein the forming of the sacrificial layer comprises: forming the sacrificial layer using at least one of an ion implantation process (IIP) using a cluster ion source and a deposition process using a plasma source with directionality given by bias application.

### Claim 5 (depends on 1)

The method of claim 1, wherein the forming of the gate patterns comprises:
forming a gate stack on the substrate and forming a second spacer on lateral surfaces of the gate stack, and the removing of the sacrificial layer comprises: exposing a portion of the second spacer.

### Claim 6 (depends on 1)

The method of claim 1, further comprising:
forming a plurality of second recesses by etching the first recesses; and
forming a plurality of semiconductor patterns in the second recesses.

### Claim 7

A method for fabricating a semiconductor device, the method comprising:
forming a plurality of gate patterns including a top portion and a bottom portion on a substrate;
forming a sacrificial layer contacting the bottom portions of the gate patterns;
forming a first spacer on lateral surfaces of the top portions of the gate patterns after forming the sacrificial layer;
removing the sacrificial layer after forming the first spacer; and
forming a plurality of first recesses at the side of the gate patterns after removing the sacrificial layer,
wherein the forming of the first spacer comprises: forming the sacrificial layer contacting the bottom portions of the gate patterns while not contacting the lateral surfaces of the top portions of the gate patterns, forming a spacer layer covering the sacrificial layer and the gate patterns on the substrate, and exposing the sacrificial layer by etching the spacer layer.

### Claim 8 (depends on 7)

The method of claim 7, wherein the forming of the first spacer further comprises: exposing a top surface of the substrate by removing the exposed sacrificial layer.

### Claim 9

A method for fabricating a semiconductor device, the method comprising:
forming a plurality of first gate patterns including a top portion and a bottom portion on a first active region of a substrate and a plurality of second gate patterns including a top portion and a bottom portion on a second active region of the substrate;
forming a sacrificial layer contacting the bottom portions of the first gate patterns;
forming a first spacer on lateral surfaces of the top portions of the first gate patterns after forming the sacrificial layer;
removing the sacrificial layer from under the first spacer after forming the first spacer; and
forming a plurality of first recesses at the side of the first gate patterns after removing the sacrificial layer.

### Claim 10 (depends on 9)

The method of claim 9, wherein the first spacer entirely overlaps the first recesses.

### Claim 11

A method for fabricating a semiconductor device, the method comprising:
forming a plurality of first gate patterns including a top portion and a bottom portion on a first active region of a substrate and a plurality of second gate patterns including a top portion and a bottom portion on a second active region of the substrate;
forming a sacrificial layer contacting the bottom portions of the first gate patterns;
forming a first spacer on lateral surfaces of the top portions of the first gate patterns after forming the sacrificial layer;
removing the sacrificial layer after forming the first spacer; and
forming a plurality of first recesses at the side of the first gate patterns after removing the sacrificial layer,
wherein the forming of the first spacer comprises: forming the sacrificial layer contacting the bottom portions of the first gate patterns while not contacting the lateral surfaces of the top portions of the first gate patterns, and forming a spacer layer covering the sacrificial layer and the first and second gate patterns on the substrate.

### Claim 12 (depends on 11)

The method of claim 11, wherein the sacrificial layer contacts the bottom portions of the second gate patterns while not contacting the top portions of the second gate patterns.

### Claim 13 (depends on 12)

The method of claim 12, wherein the forming of the first spacer comprises: forming a blocking pattern on the second active region after the forming of the spacer layer, and exposing the substrate by etching the spacer layer and the sacrificial layer on the first active region.

### Claim 14 (depends on 12)

The method of claim 12, wherein the forming of the first spacer comprises: exposing the first active region and the sacrificial layer on the second active region by etching the spacer layer, and forming a blocking pattern on the second active region after exposing the sacrificial layer.

### Claim 15 (depends on 9)

The method of claim 9, wherein the forming of the sacrificial layer comprises: forming the sacrificial layer using directional deposition.

### Claim 16

A method for fabricating a semiconductor device, the method comprising:
sequentially forming an insulation layer, an electrode layer and a hard mask layer on a first active region of a substrate and on a second active region of the substrate;
patterning the insulation layer, the electrode layer and the hard mask layer to form a plurality of first gate stacks including a first gate insulation layer, a first gate electrode and a first gate hard mask sequentially stacked on the first active region of the substrate and a plurality of second gate stacks including a second gate insulation layer, a second gate electrode and a second gate hard mask sequentially stacked on the second active region of the substrate;
forming a spacer layer covering the first gate stacks including the first gate insulation layer, the first gate electrode and the first gate hard mask and the second gate stacks including the second gate insulation layer, the second gate electrode and the second gate hard mask;
etching the spacer layer to form a first spacer on a sidewall of the first gate insulation layer, the first gate electrode and the first gate hard mask of the first gate stacks and a second spacer on a sidewall of the second gate insulation layer, the second gate electrode and the second gate hard mask of the second gate stacks to thereby respectively form a plurality of first gate patterns including a top portion and a bottom portion on the first active region of the substrate and a plurality of second gate patterns including a top portion and a bottom portion on the second active region of the substrate;
forming a sacrificial layer contacting the bottom portions of the first gate patterns but not contacting lateral surfaces of the top portions of the first gate patterns;
forming a third spacer on the lateral surfaces of the top portions of the first gate patterns after forming the sacrificial layer;
removing the sacrificial layer after forming the third spacer;
forming a plurality of first recesses at the side of the first gate patterns after removing the sacrificial layer;
forming a plurality of second recesses by etching the first recesses; and
forming a plurality of semiconductor patterns in the second recesses, wherein a portion of the semiconductors patterns are elevated relative to a top surface of the substrate, at an interface between the first gate patterns and the substrate and wherein the semiconductor patterns contact lateral surfaces of the first spacers of the first gate patterns.

### Claim 17 (depends on 16)

The method of claim 16, wherein the semiconductor patterns include a first part contacting lateral surfaces of the third spacers and a second part contacting the lateral surfaces of the first spacers of the first gate patterns and wherein a width between the first parts of the semiconductor patterns is less than a width between second parts of the semiconductor patterns.

### Claim 18 (depends on 16)

The method of claim 16, wherein the semiconductor patterns are formed through epiaxial growth of a material into the second recesses, wherein the material of the semiconductor patterns has a lattice constant different from a lattice constant of the substrate and wherein the semiconductor patterns have a sigma-shaped section.

### Claim 19 (depends on 18)

The method of claim 18, wherein the substrate is a silicon substrate and wherein the semiconductor patterns are made of silicon germanium (SiGe) having a lattice constant which is larger than a lattice constant of silicon.

### Claim 20 (depends on 18)

The method of claim 18, wherein the substrate is a silicon substrate and wherein the semiconductor patterns are made of silicon carbide (SiC) having a lattice constant which is smaller than a lattice constant of silicon.