# US 9,040,390 B2 · Releasable buried layer for 3-D fabrication and methods of manufacturing

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- Number: US 9,040,390 B2
- Document ID: US9040390B2
- Status: Granted
- Kind: B2
- Application number: 13/483,663
- Filed: 2012-05-30
- Published: 2013-12-05
- Granted: 2015-05-26
- Earliest claimed: 2012-05-30
- Assignees: International Business Machines Corporation
- Applicants: Timothy H. Daubenspeck; Steven E. Molis; Gordon C. Osborne, Jr.; Wolfgang Sauter; Edmund J. Sprogis
- Inventors: Timothy H. Daubenspeck; Steven E. Molis; Gordon C. Osborne, Jr.; Wolfgang Sauter; Edmund J. Sprogis
- Web page: https://patentgrep.com/patent/US9040390B2

## CPC

- H10P 72/74: {using temporarily an auxiliary support}
- H10W 20/074: {of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers}
- H10W 70/095: {of vias therein}
- H10W 70/635: {Through-vias}
- H10W 90/00: Package configurations
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10P 72/7412: {the auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support}
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10P 72/744: {Details of chemical or physical process used for separating the auxiliary support from a device or a wafer}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- Y10S 438/976: Temporary protective layer
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- Y10S: TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS

## Abstract

A releasable buried layer for 3-D fabrication and methods of manufacturing is disclosed. The method includes forming an interposer structure which includes forming a carbon rich dielectric releasable layer over a wafer. The method further includes forming back end of the line (BEOL) layers over the carbon rich dielectric layer, including wiring layers and solder bumps. The method further includes bonding the solder bumps to a substrate using flip chip processes. The flip chip processes comprises reflowing the solder bumps and rapidly cooling down the solder bumps which releases the carbon rich dielectric releasable layer from the wafer.

## Claims

### Claim 1

A method of forming an interposer structure, comprising:
forming a carbon rich dielectric releasable layer over a wafer;
forming back end of the line (BEOL) layers over the carbon rich dielectric layer, including wiring layers and solder bumps; and
bonding the solder bumps to a substrate using flip chip processes, wherein the flip chip processes comprises reflowing the solder bumps and rapidly cooling down the solder bumps which releases the carbon rich dielectric releasable layer from the wafer.

### Claim 2 (depends on 1)

The method of claim 1, wherein the carbon rich dielectric releasable layer is an ultra-low k dielectric layer formed using chemical vapor deposition processes.

### Claim 3 (depends on 1)

The method of claim 1, wherein the carbon rich dielectric releasable layer is formed by flooding a processing chamber with carbon at time T0.

### Claim 4 (depends on 1)

The method of claim 1, wherein the carbon rich dielectric releasable layer is a p-SiCOH film comprised of BCHD (bicycloheptadiene) and DEMS (diethoxymethylsilane).

### Claim 5 (depends on 4)

The method of claim 4, wherein a flow rate of the BCHD is turned on at time T0.

### Claim 6 (depends on 1)

The method of claim 1, wherein the carbon rich dielectric releasable layer is formed directly on an oxide film, over the wafer.

### Claim 7 (depends on 1)

The method of claim 1, wherein the cooling down comprises a cool down ramp rate of greater than 3° C./sec., with a temperature of 220° C. to 100° C.

### Claim 8 (depends on 1)

The method of claim 1, wherein the cooling down comprises a cool down ramp 2° C/sec. with a temperature of about 100° C. to ambient.

### Claim 9 (depends on 1)

The method of claim 1, wherein a carbon content of the carbon rich dielectric releasable layer is about 20% to 75% relative to other constituent components in the releasable layer.

### Claim 10 (depends on 1)

The method of claim 1, further comprising removing residue of the carbon rich dielectric releasable layer after the cooling down.

### Claim 11 (depends on 10)

The method of claim 10, further comprising bonding a package to a bond pad of the interposer, after the cooling down and removal of the residue.

### Claim 12

A method, comprising:
providing a releasable layer over a Si substrate;
forming wiring layers upon the releasable layer; and
bonding the wiring layers to a substrate using reflow processes, wherein:
the releaseable layer is formed to withstand semiconductor back end of the line processing of greater than 300° C. without detaching from the Si substrate, and
the releaseable layer is formed to detach from the Si substrate after BEOL processing,
wherein the releaseable layer comprises a p-SiCOH layer comprising BCHD (bicycloheptadiene) and DEMS (diethoxymethylsilane).

### Claim 13 (depends on 12)

The method of claim 12, further comprising flooding an initial phase of deposition of the releasable layer with a carbon-containing gas.

### Claim 14

A method, comprising:
providing a releasable layer over a Si substrate;
forming wiring layers upon the releasable layer; and
bonding the wiring layers to a substrate using reflow processes, wherein:
the releaseable layer is formed to withstand semiconductor back end of the line processing of greater than 30020 C. without detaching from the Si substrate, and
the releaseable layer is formed to detach from the Si substrate after BEOL processing,
wherein the releasable layer is a carbon rich dielectric releasable layer.

### Claim 15 (depends on 14)

The method of claim 14, wherein the releasable layer is an ultra-low k dielectric layer formed using chemical vapor deposition processes.

### Claim 16 (depends on 14)

The method of claim 14, wherein the carbon rich dielectric releasable layer is formed by flooding a chamber with carbon at time T0.

### Claim 17

A method, comprising:
providing a releasable layer over a Si substrate;
forming wiring layers upon the releasable layer; and
bonding the wiring layers to a substrate using reflow processes, wherein:
the releaseable layer is formed to withstand semiconductor back end of the line processing of greater than 300° C. without detaching from the Si substrate, and
the releaseable layer is formed to detach from the Si substrate after BEOL processing,
wherein the releaseable layer detaches from the Si substrate during a cooling down process of a solder bonding processes.

### Claim 18 (depends on 17)

The method of claim 17, wherein the cooling down comprises a cool down ramp rate of greater than 3°C./sec., with a temperature of 220° C. to 100° C. a cool down ramp 2° C/sec. with a temperature of about 100° C. to ambient.