# US 9,040,388 B2 · Chip assembly with a coreless substrate employing a patterned adhesive layer > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,040,388 B2 - Document ID: US9040388B2 - Status: Granted - Kind: B2 - Application number: 13/768,759 - Filed: 2013-02-15 - Published: 2013-06-20 - Granted: 2015-05-26 - Earliest claimed: 2010-09-09 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: Edmund Blackshear - Web page: https://patentgrep.com/patent/US9040388B2 ## CPC - H10P 90/1916: {with separation or delamination along an ion implanted layer, e.g. Smart-cut} - H10P 72/74: {using temporarily an auxiliary support} - H10W 10/181: {Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers} - H10W 74/014: {using batch processing} - H10W 72/0198: {batch processes} - H10W 72/072: {of bump connectors} - H10W 72/07204: {using temporary auxiliary members, e.g. sacrificial coatings} - H10W 72/073: {of die-attach connectors} - H10W 72/07304: {the auxiliary member being temporary, e.g. a sacrificial coating} - H10W 74/114: {by a substrate and the encapsulations} - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A patterned adhesive layer including holes is employed to attach a coreless substrate layer to a stiffener. The patterned adhesive layer is confined to kerf regions, which are subsequently removed during singulation. Each hole in the patterned adhesive layer has an area that is greater than the area of a bottomside interconnect footprint of the coreless substrate. The patterned adhesive layer may include a permanent adhesive that is thermally curable or ultraviolet-curable. The composition of the stiffener can be tailored so that the thermal coefficient of expansion of the stiffener provides tensile stress to the coreless substrate layer at room temperature and at the bonding temperature. The tensile stress applied to the coreless substrate layer prevents or reduces warpage of the coreless substrate layer during bonding. Upon dicing, bonded stacks of a semiconductor chip and a coreless substrate can be provided without adhesive thereupon. ## Claims ### Claim 1 A method of forming a bonded stack of a coreless substrate and a chip, said method comprising: forming a stack, from bottom to top, of a stiffener, a patterned adhesive layer, and a coreless substrate layer including at least one coreless substrate integrally incorporated therein, wherein said patterned adhesive layer includes a plurality of holes therein; bonding at least one chip to said at least one coreless substrate; dicing said coreless substrate layer to isolate at least one bonded stack of a coreless substrate and a chip along vertical planes that include a closed periphery that does not overlie any area of said patterned adhesive layer; applying a blanket adhesive layer to a front side of said stiffener; and applying a photoresist to said blanket adhesive layer and lithographically patterning said photoresist. ### Claim 2 (depends on 1) The method of claim 1, wherein said stiffener is diced in a same dicing process as said coreless substrate layer. ### Claim 3 A method of forming a bonded stack of a coreless substrate and a chip, said method comprising: forming a stack, from bottom to top, of a stiffener, a patterned adhesive layer, and a coreless substrate layer including at least one coreless substrate integrally incorporated therein, wherein said patterned adhesive layer includes a plurality of holes therein; bonding at least one chip to said at least one coreless substrate; and dicing said coreless substrate layer to isolate at least one bonded stack of a coreless substrate and a chip along vertical planes that include a closed periphery that does not overlie any area of said patterned adhesive layer, wherein said stiffener is not diced during said dicing of said coreless substrate layer. ### Claim 4 (depends on 1) The method of claim 1, wherein said stiffener includes a plurality of through holes therein, and said method further includes testing electrical contact between said at least one chip and said at least one coreless substrate by contacting a back side of said at least one coreless substrate through one of said plurality of through holes. ### Claim 5 (depends on 1) The method of claim 1, further comprising forming a plurality of through holes in said coreless substrate layer, wherein said at least one chip is aligned to said coreless substrate layer during said bonding employing said plurality of through holes as alignment marks. ### Claim 6 (depends on 1) The method of claim 1, further comprising forming a plurality of through holes in said stiffener, wherein said patterned adhesive layer is aligned to said stiffener employing said plurality of through holes as alignment marks. ### Claim 7 A method of forming a bonded stack of a coreless substrate and a chip, said method comprising: forming a stack, from bottom to top, of a stiffener, a patterned adhesive layer, and a coreless substrate layer including at least one coreless substrate integrally incorporated therein, wherein said patterned adhesive layer includes a plurality of holes therein; bonding at least one chip to said at least one coreless substrate; dicing said coreless substrate layer to isolate at least one bonded stack of a coreless substrate and a chip along vertical planes that include a closed periphery that does not overlie any area of said patterned adhesive layer; applying a blanket adhesive layer to a back side surface of said coreless substrate layer; and applying a photoresist to said blanket adhesive layer and lithographically patterning said photoresist. ### Claim 8 (depends on 1) The method of claim 1, wherein bonding said at least one chip to said at least one coreless substrate comprises using C4 balls. ### Claim 9 (depends on 1) The method of claim 1, wherein said stiffener applies lateral tensile stress to said coreless substrate layer at least at room temperature and at a temperature selected from a range between 210 degrees Celsius and 300 degrees Celsius. ### Claim 10 (depends on 1) The method of claim 1, wherein said patterned adhesive layer includes a thermally cured adhesive material, an ultraviolet cured adhesive material, or a combination thereof. ### Claim 11 (depends on 1) The method of claim 1, wherein said stiffener is composed of a material having a glass transition temperature between 150 degrees Celsius and 210 degrees Celsius. ### Claim 12 (depends on 9) The method of claim 9, wherein said stiffener is composed of a material having a first temperature-dependent coefficient of thermal expansion that is greater than a second temperature-dependent coefficient of thermal expansion of said coreless substrate above a cross-over temperature and is less than said second temperature-dependent coefficient of thermal expansion below said cross-over temperature, wherein said cross-over temperature is between 150 degrees Celsius and 210 degrees Celsius. ### Claim 13 (depends on 12) The method of claim 12, wherein said stiffener is composed of epoxy resin or polyimide. ### Claim 14 (depends on 1) The method of claim 1, wherein said coreless substrate layer and said stiffener are vertically spaced from each other by said patterned adhesive layer. ### Claim 15 (depends on 14) The method of claim 14, wherein a vertical distance between said coreless substrate layer and said stiffener is the same as a thickness of said patterned adhesive layer. ### Claim 16 (depends on 1) The method of claim 1, wherein said patterned adhesive layer and said plurality of chips are vertically spaced from each other by said coreless substrate layer. ### Claim 17 (depends on 16) The method of claim 16, wherein a vertical distance between said patterned adhesive layer and said plurality of chips is the same as a thickness of said coreless substrate layer.