# US 9,040,387 B2 · Stacked microelectronic packages having patterned sidewall conductors and methods for the fabrication thereof

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- Number: US 9,040,387 B2
- Document ID: US9040387B2
- Status: Granted
- Kind: B2
- Application number: 13/591,969
- Filed: 2012-08-22
- Published: 2014-02-27
- Granted: 2015-05-26
- Earliest claimed: 2012-08-22
- Assignees: Freescale Semiconductor, Inc.
- Applicants: Zhiwei Gong; Michael B Vincent; Scott M Hayes; Jason R Wright
- Inventors: Zhiwei Gong; Michael B Vincent; Scott M Hayes; Jason R Wright
- Web page: https://patentgrep.com/patent/US9040387B2

## CPC

- H01L 23/5389
- H01L 21/78
- H01L 23/48
- H01L 23/3128
- H01L 23/49805
- H01L 23/49838
- H01L 21/561
- H01L 25/105
- H01L 2224/48091
- H01L 2924/00014
- H01L 24/48
- H01L 24/24
- H01L 24/82
- H01L 24/96
- H01L 2224/24145
- H01L 2924/18165
- H01L 2924/1461
- H01L 2224/45099
- H01L 2924/00
- H01L

## Abstract

Embodiments of a method for fabricating stacked microelectronic packages are provided, as are embodiments of a stacked microelectronic package. In one embodiment, the method includes arranging microelectronic device panels in a panel stack. Each microelectronic device panel includes a plurality of microelectronic devices and a plurality of package edge conductors extending therefrom. Trenches are formed in the panel stack exposing the plurality of package edge conductors. An electrically-conductive material is deposited into the trenches and contacts the plurality of package edge conductors exposed therethrough. The panel stack is then separated into partially-completed stacked microelectronic packages. For at least one of the partially-completed stacked microelectronic packages, selected portions of the electrically-conductive material are removed to define a plurality of patterned sidewall conductors interconnecting the microelectronic devices included within the stacked microelectronic package.

## Claims

### Claim 1

A method for fabricating stacked microelectronic packages, comprising:
arranging microelectronic device panels in a panel stack, each microelectronic device panel comprising a plurality of microelectronic devices and a plurality of package edge conductors extending therefrom;
forming trenches in the panel stack, the trenches having sidewalls through which the plurality of package edge conductors are exposed;
dispensing a metal-containing epoxy into the trenches in sufficient quantity to substantially fill the trenches and yield a plurality of epoxy-filled trenches
separating the panel stack into partially-completed stacked microelectronic packages to produce unpatterned metal-containing epoxy layers contacting the plurality of package edge conductors, the panel stack separated along saw lanes extending through the epoxy-filled trenches to impart the unpatterned metal-containing epoxy layers with exposed sidewall surfaces; and
patterning the unpatterned metal-containing epoxy layers to define a plurality of patterned sidewall conductors interconnecting the microelectronic devices included within the stacked microelectronic packages, wherein selected portions of the unpatterned metal-containing epoxy layers are removed at the exposed sidewall surfaces during patterning.

### Claim 2 (depends on 1)

A method according to claim 1 wherein removing comprises patterning the unpatterned metal-containing epoxy layers using a laser ablation process.

### Claim 3 (depends on 1)

A method according to claim 1 wherein each of the plurality of microelectronic device panels is produced using a process comprising:
embedding microelectronic devices in an encapsulant having a device surface through which the microelectronic devices are exposed; and
forming the package edge conductors over the device surface and electrically coupled to the microelectronic devices.

### Claim 4 (depends on 1)

A method according to claim 1 further comprising depositing a dielectric material between neighboring ones of the plurality of sidewall conductors.

### Claim 5 (depends on 1)

A method according to claim 1 wherein each microelectronic device panels comprises dicing streets to which the plurality of package edge conductors extend, and wherein the step of arranging comprises arranging the device panels in a panel stack such that the dicing streets of the device panels at least partially overlap, as taken along a centerline of the panel stack.

### Claim 6 (depends on 5)

A method according to claim 5 wherein forming comprises cutting non-penetrating trenches into the panel stack along the dicing streets and transecting the plurality of package edge conductors.

### Claim 7 (depends on 6)

A method according to claim 6 wherein cutting comprises cutting non-penetrating trenches into the panel stack having a first predetermined width, and wherein separating comprises singulating the panel stack into a plurality of stacked microelectronic packages utilizing a saw blade having thickness less than the first predetermined width.

### Claim 8 (depends on 1)

A method according to claim 1 wherein the unpatterned paste layers are patterned subsequent to separation of the panel stack into partially-completed stacked microelectronic packages.

### Claim 9 (depends on 1)

A method according to claim 1 wherein each microelectronic device panel further comprises one or more layers of dielectric material overlying the plurality of microelectronic devices and in which the plurality of edge conductors extend.

### Claim 10 (depends on 2)

A method according to claim 2 wherein the laser ablation process is carried-out at laser energy levels less than about 4 Watts.

### Claim 11

A method for fabricating a stacked microelectronic package, comprising:
obtaining a partially-completed stacked microelectronic package having at least upper and lower package layers, the upper and lower package layers each comprising:
a package body;
a microelectronic device embedded in the package body; and
one or more dielectric layers overlying the package body and the microelectronic device; and
a plurality of package edge conductors formed in the one or more dielectric layers and extending from the microelectronic device to a sidewall of the stacked microelectronic package, the plurality of package edge conductors exposed through the sidewall of the stacked microelectronic package;
producing an unpatterned metal-containing epoxy layer contacting the plurality of package edge conductors by dispensing a metal-containing epoxy over the sidewall of the package body, curing the metal-containing epoxy, and cutting through the metal-containing epoxy during package singulation; and
patterning the unpatterned metal-containing epoxy layer by removing selected portions of the electrically-conductive layer at one or more surfaces created when cutting through the metal-containing epoxy layer during package singulation, the unpatterned metal-containing epoxy layer patterned to produce a plurality of sidewall conductors interconnecting the microelectronic devices included within the upper and lower package layers.

### Claim 12 (depends on 8)

A method according to claim 8 wherein the unpatterned paste layers cover at least one side of each partially-completed stacked microelectronic packages.

### Claim 13 (depends on 8)

A method according to claim 8 wherein the unpatterned paste layers extend around all four sides of each partially-completed stacked microelectronic packages.