# US 9,040,383 B2 · Devices with gate-to-gate isolation structures and methods of manufacture

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- Number: US 9,040,383 B2
- Document ID: US9040383B2
- Status: Granted
- Kind: B2
- Application number: 13/772,993
- Filed: 2013-02-21
- Published: 2013-06-27
- Granted: 2015-05-26
- Earliest claimed: 2010-10-12
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Brent A. Anderson; Edward J. Nowak; Jed H. Rankin
- Web page: https://patentgrep.com/patent/US9040383B2

## CPC

- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 86/011: {comprising FinFETs}
- H10P 90/1906: {Preparing SOI wafers}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/061: {using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10W 10/181: {Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Devices having gate-to-gate isolation structures and methods of manufacture are provided. The method includes forming a plurality of isolation structures in pad films and an underlying substrate. The method further includes forming a plurality of fins including the isolation structures and a second plurality of fins including the two pad films and a portion of the underlying substrate, each of which are separated by a trench. The method further includes removing portions of the second plurality of fins resulting in a height lower than a height of the plurality of fins including the isolation structures. The method further includes forming gate electrodes within each trench, burying the second plurality of fins and abutting sides of the plurality of fins including the isolation structures. The plurality of fins including the isolation structures electrically and physically isolate adjacent gate electrode of the gate electrodes.

## Claims

### Claim 1

A method, comprising:
forming a plurality of isolation structures in pad films and an underlying substrate;
forming a plurality of fins comprising the isolation structures and a second plurality of fins comprising two pad films and a portion of the underlying substrate, each of which are separated by a trench;
removing portions of the second plurality of fins resulting in a height lower than a height of the plurality of fins comprising the isolation structures;
forming gate electrodes within each trench, burying the second plurality of fins and abutting sides of the plurality of fins comprising the isolation structures; and
etching a portion of one of the gate electrodes, at a location between two of the fins comprising the isolation structures and over the second plurality of fins, such that an upper surface of the one of the gate electrodes is lower than the two of the fins comprising the isolation structures and higher than the second plurality of fins,
wherein the plurality of fins comprising the isolation structures electrically and physically isolate adjacent gate electrode of the gate electrodes.

### Claim 2 (depends on 1)

The method of claim 1, wherein the underlying substrate is a BULK wafer.

### Claim 3 (depends on 1)

The method of claim 1, wherein the underlying substrate is a Silicon on Insulator (SOI), and each trench is formed by etching to an insulator layer of the SOI.

### Claim 4 (depends on 1)

The method of claim 1, wherein the pad films are deposited on the underlying substrate and trenches are formed in the pad films and portion of the underlying substrate, which are filled with insulator material to form the isolation structures.

### Claim 5 (depends on 4)

The method of claim 4, wherein an upper pad film of the second plurality of fins is Si3N4.

### Claim 6 (depends on 5)

The method of claim 5, wherein a lower pad film of the second plurality of fins is at least SiO2.

### Claim 7 (depends on 1)

The method of claim 1, wherein the removing portions of the second plurality of fins forms a stepped structure, with remaining portions of the second plurality of fins being lower than at least one of the plurality of isolation structures with respect to a surface of the underlying substrate.

### Claim 8 (depends on 1)

The method of claim 1, wherein the plurality of fins comprising the isolation structures have a width of about 10 nm.

### Claim 9 (depends on 1)

The method of claim 1, wherein the plurality of fins comprising the isolation structures have uniform spacing therebetween in a regular pattern.

### Claim 10 (depends on 1)

The method of claim 1, wherein the adjacent gate electrodes are formed by deposition and etching processes.

### Claim 11 (depends on 10)

The method of claim 10, wherein the etching of the adjacent gate electrodes is to a level lower than the plurality of fins comprising the isolation structures.

### Claim 12 (depends on 1)

The method of claim 1, wherein the plurality of fins comprising the isolation structures have heights corresponding to adjacent gate electrodes, said heights of the isolation structures isolating the adjacent gate electrodes at a minimum image spacing.

### Claim 13 (depends on 1)

The method of claim 1, wherein:
the forming the plurality of fins comprising the isolation structures and a second plurality of fins comprises masking and etching to form the trenches, each the plurality of fins comprising the isolation structures and a second plurality of fins have two vertical sidewalls formed by the trenches; and
the removing portions of the second plurality of fins includes selectively removing an upper one of the pad films,
wherein the etching is selective to the upper one of the pad films.

### Claim 14

A method comprising:
forming a plurality of pad films each having different material compositions on a substrate;
etching the pad films and a portion of the substrate to form a plurality of trenches;
filling the trenches with insulator material to form a plurality of isolation structures;
forming a second plurality of trenches which result in the formation of a plurality of fins comprising the isolation structures and a second plurality of composite fins comprising the plurality of pad films and the portion of the substrate;
removing an upper portion of the plurality of composite fins resulting in a height different than the plurality of fins comprising the isolation structures; and
forming gate electrode stacks within each of the second plurality of trenches, burying the plurality of composite fins and abutting sides of the plurality of fins comprising the isolation structures, wherein the plurality of fins comprising the isolation structures electrically and physically isolate adjacent electrode stacks,
wherein the gate electrode stacks are formed over and around the second plurality of fins comprising one of the two pad films and the portion of the underlying substrate, and an upper surface of the gate electrode stacks is lower than the two of the fins comprising the isolation structures and higher than the second plurality of fins.

### Claim 15 (depends on 14)

The method of claim 14, wherein the underlying substrate is a BULK wafer.

### Claim 16 (depends on 14)

The method of claim 14, wherein the underlying substrate is a Silicon on Insulator (SOI), and each trench forming the isolation structures and each trench of the second plurality of trenches is formed by etching to an insulator layer of the SOI.

### Claim 17 (depends on 14)

The method of claim 14, wherein an upper pad film is Si3N4 and a lower pad film is SiO2 for subsequent selective etching processes.

### Claim 18 (depends on 14)

The method of claim 14, wherein the plurality of fins comprising the isolation structures have a width of about 10 nm.

### Claim 19 (depends on 14)

The method of claim 14, wherein the adjacent electrode stacks are formed by deposition and etching processes.

### Claim 20 (depends on 14)

The method of claim 14, wherein the plurality of fins comprising the isolation structures have heights corresponding to adjacent gate electrodes, said heights of the isolation structures isolating the adjacent gate electrodes at a minimum image spacing.