# US 9,040,381 B2 · Packages with passive devices and methods of forming the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,040,381 B2 - Document ID: US9040381B2 - Status: Granted - Kind: B2 - Application number: 14/080,014 - Filed: 2013-11-14 - Published: 2014-03-13 - Granted: 2015-05-26 - Earliest claimed: 2011-12-29 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company, Ltd. - Inventors: Chen-Hua Yu; Shang-Yun Hou; Der-Chyang Yeh; Shuo-Mao Chen; Chiung-Han Yeh; Yi-Jou Lin - Web page: https://patentgrep.com/patent/US9040381B2 ## CPC - H10W 74/01: Manufacture or treatment - H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs - H10W 70/614: {the multiple chips being integrally enclosed} - H10W 70/685: comprising multiple insulating layers - H10W 70/69: Insulating materials thereof - H10W 74/147: {the encapsulations being multilayered} - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10D 1/00: Resistors, capacitors or inductors - H10D 86/85: characterised by only passive components - H10W 44/00: Electrical arrangements for controlling or matching impedance - H10W 72/072: {of bump connectors} - H10W 72/073: {of die-attach connectors} - H10W 72/241: {Dispositions, e.g. layouts} - H10W 72/29: Bond pads specially adapted therefor - H10W 72/9413: {on encapsulations} - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body} - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A device includes a substrate, a metal pad over the substrate, and a passivation layer having a portion over the metal pad. A Post-Passivation Interconnect (PPI) line is disposed over the passivation layer and electrically coupled to the metal pad. An Under-Bump Metallurgy (UBM) is disposed over and electrically coupled to the PPI line. A passive device includes a portion at a same level as the UBM. The portion of the passive device is formed of a same material as the UBM. ## Claims ### Claim 1 A method comprising: molding a die in a polymer, with the polymer encircling the die; planarizing the polymer to expose a metal pillar of the die; forming a Post-Passivation Interconnect (PPI) line over and electrically coupled to the metal pillar; forming an Under-Bump Metallurgy (UBM) over and electrically coupled to the PPI line; forming a first portion of a passive device, wherein the first portion of the passive device and the UBM are formed simultaneously; and forming a solder ball on the UBM. ### Claim 2 (depends on 1) The method of claim 1 further comprising: before the forming the UBM, forming a Post-Passivation Interconnect (PPI) line, with the UBM electrically coupled to the metal pillar through the PPI line; and forming a second portion of the passive device, wherein the second portion of the passive device and the PPI line are formed simultaneously. ### Claim 3 (depends on 1) The method of claim 1 further comprising: after the planarizing the polymer, forming a dielectric layer overlying and contacting the polymer and the die; forming a via in the dielectric layer, wherein the via comprises an electrically conductive material; and forming a third portion of the passive device, wherein the third portion of the passive device and the via are formed simultaneously. ### Claim 4 (depends on 1) The method of claim 1, wherein the first portion of the passive device comprises a portion overlapping the polymer. ### Claim 5 (depends on 1) The method of claim 1 further comprising: forming a dielectric mask layer over the passive device and the UBM; and patterning the dielectric mask layer to expose the solder ball, wherein the passive device is covered by a remaining portion of the dielectric mask layer. ### Claim 6 (depends on 1) The method of claim 1 further comprising: bonding the solder ball to a package component; and dispensing an underfill into a gap between the die and the package component, wherein the underfill contacts the passive device. ### Claim 7 (depends on 1) The method of claim 1, wherein the solder ball is in direct contact with the UBM. ### Claim 8 (depends on 1) The method of claim 1 further comprising forming a dielectric layer comprising a portion over the PPI line, wherein the UBM comprises a portion over and aligned to the dielectric layer. ### Claim 9 A method comprising: attaching a die over a carrier, wherein the die comprises: a semiconductor substrate; a metal pad over the semiconductor substrate; a passivation layer comprising a portion over the metal pad; and a metal pillar over the metal pad and extending into the passivation layer; molding the die in a polymer, with the polymer encircling the die; forming a first dielectric layer over the metal pillar, the passivation layer, and the polymer; forming first openings in the first dielectric layer, wherein the metal pillar is exposed through one of the first openings; forming a Post-Passivation Interconnect (PPI) line, wherein the PPI line is electrically coupled to the metal pad through the metal pillar and a via in the one of the first openings; forming a second dielectric layer comprising a portion over the PPI line; forming an Under-Bump Metallurgy (UBM) over and electrically coupled to the PPI line; forming a solder region over and connected to the UBM; and forming a first portion of a passive device, wherein the first portion of a passive device and the UBM are formed simultaneously. ### Claim 10 (depends on 9) The method of claim 9, wherein the first openings comprise portions over and aligned to the polymer, and wherein at a time the PPI line is formed, a metallic material is filled into portions of the first openings to form a second portion of the passive device. ### Claim 11 (depends on 9) The method of claim 9, wherein the passive device comprises a resistor, a capacitor, an inductor, a transformer, a balun, a micro-stripe, or a co-planar waveguide. ### Claim 12 (depends on 9) The method of claim 9 further comprising: forming a dielectric mask layer over the passive device and the UBM; and patterning the dielectric mask layer to expose the solder region, wherein the passive device is covered by a remaining portion of the dielectric mask layer. ### Claim 13 (depends on 9) The method of claim 9 further comprising: bonding the solder region to a package component; and dispensing an underfill into a gap between the second dielectric layer and the package component, wherein the underfill contacts the passive device. ### Claim 14 (depends on 9) The method of claim 9 further comprising, before the step of forming the first dielectric layer, performing a grinding step to level a top surface of the metal pillar, the passivation layer, and the polymer. ### Claim 15 (depends on 9) The method of claim 9, wherein the first portion of the passive device comprises a portion overlapping the polymer. ### Claim 16 (depends on 9) The method of claim 9, wherein the passive device comprises a top surface level with a top surface of the UBM, and a bottom surface level with a top surface of the metal pillar. ### Claim 17 A method comprising: molding a die with a polymer, with the polymer encircling the die; planarizing the polymer to expose a metal pillar of the die; forming a Post-Passivation Interconnect (PPI) line over and electrically coupled to the metal pillar; forming an Under-Bump Metallurgy (UBM) over and electrically coupled to the PPI line; forming a first portion of a passive device, wherein a first portion of the passive device and the UBM are formed simultaneously in a same process step, and wherein the first portion of the passive device comprises a portion overlapping the polymer; and forming a solder ball over and in physical contact with the UBM. ### Claim 18 (depends on 17) The method of claim 17 further comprising: forming a dielectric layer over the PPI line, with a portion of the UBM over and contacting the dielectric layer; and forming a second portion of the passive device, wherein the second portion of the passive device and the PPI line are formed simultaneously in a same additional process step. ### Claim 19 (depends on 17) The method of claim 17, wherein the passive device comprises a resistor, a capacitor, an inductor, a transformer, a balun, a micro-stripe, or a co-planar waveguide. ### Claim 20 (depends on 17) The method of claim 17, wherein the passive device comprises a top surface level with a top surface of the UBM, and a bottom surface level with a top surface of the metal pillar.