# US 9,040,380 B2 · Integrated circuits having laterally confined epitaxial material overlying fin structures and methods for fabricating same

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- Number: US 9,040,380 B2
- Document ID: US9040380B2
- Status: Granted
- Kind: B2
- Application number: 14/023,558
- Filed: 2013-09-11
- Published: 2015-03-12
- Granted: 2015-05-26
- Earliest claimed: 2013-09-11
- Assignees: Globalfoundries Inc.
- Applicants: GLOBALFOUNDRIES, Inc.
- Inventors: Xiang Hu; Jin Ping Liu; Jill Hildreth; Taejoon Han
- Web page: https://patentgrep.com/patent/US9040380B2

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/0158: {the components including FinFETs}
- H10D 86/011: {comprising FinFETs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a fin structure overlying a semiconductor substrate. The fin structure defines a fin axis extending in a longitudinal direction perpendicular to a lateral direction and has two fin sidewalls parallel to the fin axis. The method includes forming gate structures overlying the fin structure and transverse to the fin axis. Further, the method includes growing an epitaxial material on the fin structure and confining growth of the epitaxial material in the lateral direction.

## Claims

### Claim 1

A method for fabricating an integrated circuit comprising:
providing a fin structure overlying a semiconductor substrate, wherein the fin structure defines a fin axis extending in a longitudinal direction perpendicular to a lateral direction, wherein the fin structure has two fin sidewalls parallel to the fin axis, and wherein the fin structure has a top surface extending between the fin sidewalls;
forming gate structures overlying the fin structure and transverse to the fin axis; and
growing an epitaxial material on the top surface of the fin structure while preventing growth of the epitaxial material on the fin sidewalls and confining growth of the epitaxial material over the top surface in the lateral direction.

### Claim 2 (depends on 1)

The method of claim 1 further comprising confining growth of the epitaxial material in the longitudinal direction.

### Claim 3 (depends on 1)

The method of claim 1 wherein:
providing the fin structure overlying a semiconductor substrate comprises providing selected fin structures and non-selected fin structures;
forming gate structures overlying the fin structure comprises forming gate structures overlying the selected fin structures and the non-selected fin structures; and
growing the epitaxial material on the top surface of the fin structure comprises growing the epitaxial material on selected fin structures while preventing growth of the epitaxial material on the non-selected fin structures.

### Claim 4 (depends on 1)

The method of claim 1 further comprising forming barrier walls overlying the semiconductor substrate, wherein each barrier wall is aligned with a respective fin sidewall, wherein confining growth of the epitaxial material in the lateral direction comprises confining growth of the epitaxial material in the lateral direction with each barrier wall.

### Claim 5 (depends on 4)

The method of claim 4 wherein forming barrier walls overlying the semiconductor substrate comprises forming each barrier wall in contact with each gate structure.

### Claim 6 (depends on 4)

The method of claim 4 further comprising depositing a liner overlying the gate structures and the fin structure, wherein forming barrier walls overlying the semiconductor substrate comprises:
depositing a dielectric material overlying the semiconductor substrate; and
etching a trench in the dielectric material and a portion of the liner overlying the fin structure and exposing the fin structure between the gate structures, wherein the trench is defined by the barrier walls, wherein growing epitaxial material on the fin structure and confining the epitaxial material by the barrier walls comprises growing epitaxial material in the trench.

### Claim 7 (depends on 4)

The method of claim 4 further comprising depositing a liner overlying the gate structures and the fin structure, wherein forming barrier walls overlying the semiconductor substrate comprises:
depositing a dielectric material overlying the semiconductor substrate; and
etching a trench in the dielectric material and a portion of the liner overlying the fin structure and exposing the fin structure between the gate structures, wherein the trench is defined by the barrier walls, wherein growing epitaxial material on the fin structure and confining the epitaxial material by the barrier walls comprises growing epitaxial material in the trench, and wherein growing epitaxial material on the fin structure and confining the epitaxial material with the barrier walls further comprises confining the epitaxial material with remaining portions of the liner adjacent the gate structures.

### Claim 8 (depends on 4)

The method of claim 4 wherein forming barrier walls overlying the semiconductor substrate comprises:
depositing a dielectric material overlying the semiconductor substrate; and
etching a trench in the dielectric material and defining an exposed portion of the fin structure between the gate structures, wherein the trench is defined by the barrier walls, and wherein the method further comprises etching the exposed portion of the fin structure before growing epitaxial material on the fin structure.

### Claim 9 (depends on 4)

The method of claim 4 wherein forming barrier walls overlying the semiconductor substrate comprises:
depositing a dielectric material overlying the semiconductor substrate; and
etching a trench in the dielectric material and exposing the fin structure between the gate structures, wherein the trench is defined by the barrier walls, wherein growing epitaxial material on the fin structure and confining the epitaxial material by the barrier walls comprises growing epitaxial material in the trench, and wherein the method further comprises depositing additional dielectric material in the trench over the epitaxial material.

### Claim 10 (depends on 4)

The method of claim 4 further comprising depositing additional dielectric material over the epitaxial material and between the barrier walls.

### Claim 11 (depends on 4)

The method of claim 4 wherein forming barrier walls overlying the semiconductor substrate comprises:
depositing a dielectric material overlying the semiconductor substrate; and
etching a trench in the dielectric material and exposing the fin structure between the gate structures, wherein the trench is defined by the barrier walls, wherein growing epitaxial material on the fin structure and confining the epitaxial material by the barrier walls comprises growing epitaxial material in the trench.

### Claim 12 (depends on 11)

The method of claim 11 wherein etching a trench in the dielectric material comprises:
forming a patterned mask overlying the dielectric material to define an exposed region of the dielectric material; and
etching the exposed region of the dielectric material.

### Claim 13

A method for fabricating an integrated circuit comprising:
providing fin structures overlying a semiconductor substrate, wherein each fin structure has fin sidewalls parallel to a fin axis extending in a longitudinal direction perpendicular to a lateral direction;
forming gate structures overlying the fin structures and transverse to the fin axis;
depositing a dielectric material overlying the gate structures and fin structures, wherein the dielectric material covers selected fin structures and non-selected fin structures;
etching trenches into the dielectric material to expose the selected fin structures; and
growing an epitaxial material on the selected fin structures and confining growth of the epitaxial material in the lateral direction with the dielectric material while covering the non-selected fin structures with the dielectric material.

### Claim 14 (depends on 13)

The method of claim 13 wherein etching trenches into the dielectric material comprises etching portions of the selected fin structures.

### Claim 15 (depends on 13)

The method of claim 13 further comprising confining growth of the epitaxial material in the longitudinal direction.

### Claim 16 (depends on 13)

The method of claim 13 wherein:
etching trenches into the dielectric material comprises forming barrier walls overlying the semiconductor substrate, wherein each barrier wall is aligned with a respective fin sidewall; and
growing epitaxial material on the selected fin structures and confining growth of the epitaxial material in the lateral direction with the dielectric material comprises confining growth of the epitaxial material in the lateral direction with each barrier wall.

### Claim 17 (depends on 13)

The method of claim 13 wherein etching trenches into the dielectric material comprises:
forming a patterned mask overlying the dielectric material to define exposed regions of the dielectric material; and
etching the exposed regions of the dielectric material.

### Claim 18 (depends on 13)

The method of claim 13 wherein
etching trenches into the dielectric material comprises exposing top surfaces of the selected fin structures while the sidewalls of the selected fin structures remain covered by the dielectric material; and
growing the epitaxial material comprises growing the epitaxial material on the top surfaces of the selected fin structures while preventing growth of the dielectric material on the fin sidewalls and confining growth of the epitaxial material over the top surfaces in the lateral direction with the dielectric material.

### Claim 19 (depends on 18)

The method of claim 18 wherein:
etching trenches into the dielectric material comprises etching the liner overlying the selected fin structures and exposing the liner overlying portions of the gate structures overlying the selected fin structures; and
growing epitaxial material on the selected fin structures comprises confining growth of the epitaxial material in the longitudinal direction with the liner overlying portions of the gate structures overlying the selected fin structures.

### Claim 20

An integrated circuit comprising:
a semiconductor substrate;
a fin structure overlying the semiconductor substrate and having two sidewalls parallel to a fin axis and a top surface extending between the sidewalls at a height over the semiconductor substrate;
a gate structure overlying the fin structure and defining a channel region and source/drain regions in the fin structure; and
epitaxial material overlying the top surface of the fin structure at the source/drain regions, wherein the epitaxial material has side surfaces substantially parallel to the fin axis and substantially perpendicular to the semiconductor substrate, wherein each side surface extends downward from an upper edge and terminates at the height of the fin structure.