# US 9,040,379 B2 · Semiconductor constructions and methods of forming semiconductor constructions

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 9,040,379 B2
- Document ID: US9040379B2
- Status: Granted
- Kind: B2
- Application number: 14/168,898
- Filed: 2014-01-30
- Published: 2014-05-29
- Granted: 2015-05-26
- Earliest claimed: 2012-05-25
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Zengtao T. Liu
- Web page: https://patentgrep.com/patent/US9040379B2

## CPC

- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/074: {of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers}
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10B 12/053: {the transistor being at least partially in a trench in the substrate (vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383)}
- H10B 12/09: {with simultaneous manufacture of the peripheral circuit region and memory cells}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

Some embodiments include methods in which first insulative material is formed across a memory region and a peripheral region of a substrate. An etch stop structure is formed to have a higher portion over the memory region than over the peripheral region. A second insulative material is formed to protect the lower portion of the etch stop structure, and the higher portion is removed. Subsequently, at least some of the first and second insulative materials are removed. Some embodiments include semiconductor constructions having a first region with first features, and a second region with second features. The first features are closer spaced than the second features. A first insulative material is over the second region and an insulative structure is over the first insulative material. The structure has a stem joined to a bench. The bench has an upper surface, and the stem extends to above the upper surface.

## Claims

### Claim 1

A semiconductor construction, comprising:
a first region of a silicon-containing substrate having first features, and a second region of the silicon-containing substrate having second features; the first features being more closely spaced than the second features; the first region interfacing with the second region along an electrically insulative material;
a first insulative material over the second region, and having a top surface below upper surfaces of the first features;
a second insulative material over the first insulative material and having a different composition from the first insulative material; the second insulative material being configured as a structure having an upwardly-extending stem joined to a horizontally-extending bench; the bench having an upper surface at about a common level as upper surfaces of the first features; the stem extending to above the upper surfaces of the first features; and
a conductive material within the second region and extending through the first and second insulative materials.

### Claim 2 (depends on 1)

The construction of claim 1 wherein the first features are conductive lines covered by silicon nitride caps; and wherein the second insulative material is silicon nitride.

### Claim 3 (depends on 2)

The construction of claim 2 wherein the conductive lines are over, and electrically coupled with, source regions of access transistors.

### Claim 4 (depends on 2)

The construction of claim 2 wherein the first insulative material is silicon dioxide.

### Claim 5

A semiconductor construction, comprising:
a memory region, and a peripheral region adjacent the memory region; the regions being comprised by a semiconductor substrate;
spaced-apart conductive structures within the memory region;
insulative caps over the conductive structures;
a first insulative material over the peripheral region, and having a top surface below upper surfaces of the insulative caps;
a second insulative material over the first insulative material and having a different composition from the first insulative material; the second insulative material being configured as a structure having an upwardly-extending stem joined to a horizontally-extending bench; the bench having an upper surface at about a common level as upper surfaces of the insulative caps; the stem extending to above the upper surfaces of the insulative caps; and
a plug within the peripheral region and extending through the first and second insulative materials.

### Claim 6 (depends on 5)

The construction of claim 5 wherein the conductive structures are lines.

### Claim 7 (depends on 5)

The construction of claim 5 wherein the conductive structures are lines extending over, and electrically coupled with, source regions of access transistors.

### Claim 8 (depends on 5)

The construction of claim 5 wherein the insulative caps and the second insulative material comprise a common composition.

### Claim 9

A semiconductor construction, comprising:
a first region of a silicon-containing substrate having first features, and a second region of the silicon-containing substrate having second features; the first and second features being conductive, and comprising a same conductive composition as one another;
a first insulative material over the second region, and having a top surface below upper surfaces of the first features;
a second insulative material over the first insulative material and having a different composition from the first insulative material; the second insulative material being configured as a structure having an upwardly-extending stem joined to a horizontally-extending bench; the bench having an upper surface at about a common level as upper surfaces of the first features; the stem extending to above the upper surfaces of the first features; and
a conductive plug within the second region and extending through the first and second insulative materials to contact a conductive material which is under the first insulative material.