# US 9,040,376 B2 · Semiconductor device and method for manufacturing the same

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- Number: US 9,040,376 B2
- Document ID: US9040376B2
- Status: Granted
- Kind: B2
- Application number: 14/044,475
- Filed: 2013-10-02
- Published: 2014-12-18
- Granted: 2015-05-26
- Earliest claimed: 2013-06-14
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Suk Ki Kim; Kang Sik Choi
- Web page: https://patentgrep.com/patent/US9040376B2

## CPC

- H10D 30/0212: {using self-aligned silicidation}
- H10B 63/34: {of the vertical channel field-effect transistor type}
- H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)}
- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 64/01: Manufacture or treatment
- H10D 84/016: {the components including vertical IGFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A semiconductor device forms a salicide layer to surround an upper surface and a circumference of a lateral surface of a pillar. A contact area between the pillar and a lower electrode may be increased to reduce a contact resistance.

## Claims

### Claim 1

A method for manufacturing a semiconductor device, the method comprising:
forming a plurality of pillars by etching a semiconductor substrate using a hard mask pattern;
gap-filling a conductive material between the pillars, and etching back the conductive material so that an upper surface of the etching backed conductive material has a height lower than that of an upper surface of each of the pillars;
forming a first spacer on a lateral surface of the hard mask pattern and on an upper portion of a lateral surface of each of pillars, which is uncovered with the etching backed conductive material, the first spacer formed of the same material as that of the hard mask pattern;
removing the hard mask pattern and an upper portion of the first spacer to expose the upper surface of each of the pillars and a portion of the upper portion of the lateral surface of each of the pillars;
forming a salicide layer to surround the exposed upper surface of each of the pillars and the exposed portion of the upper portion of the lateral surface of each of the pillars; and
forming a lower electrode to surround the salicide layer.

### Claim 2 (depends on 1)

The method of claim 1, further comprising forming a gate insulating layer on the semiconductor substrate including the pillars, after the forming of the pillars in the semiconductor substrate.

### Claim 3 (depends on 1)

The method of claim 1, wherein the first spacer includes a material having the same etch selectivity as or a similar etch selectivity to that of the hard mask pattern.

### Claim 4 (depends on 3)

The method of claim 3, further comprising forming a second spacer surrounding a lateral surface of the first spacer after the forming of the first spacer.

### Claim 5 (depends on 2)

The method of claim 2, wherein a upper portion of the gate insulating layer is removed in the removing of the hard mask pattern and the upper portion of the first spacer.

### Claim 6 (depends on 4)

The method of claim 4, further comprising removing the etching backed conductive material, after the forming of the second spacer.

### Claim 7 (depends on 6)

The method of claim 6, further comprising forming an inter-cell insulating layer by gap-filling an insulating layer on the semiconductor substrate from which the etching backed conductive material is removed and planarizing the insulating layer, after the removing of the etching backed conductive material.