# US 9,040,375 B2 · Method for processing a carrier, method for fabricating a charge storage memory cell, method for processing a chip, and method for electrically contacting a spacer structure > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,040,375 B2 - Document ID: US9040375B2 - Status: Granted - Kind: B2 - Application number: 13/751,185 - Filed: 2013-01-28 - Published: 2014-07-31 - Granted: 2015-05-26 - Earliest claimed: 2013-01-28 - Assignees: Infineon Technologies Dresden GmbH - Applicants: Infineon Technologies Dresden GmbH - Inventors: Robert Strenz; Mayk Roehrich; Wolfram Langheinrich; John Power; Danny Shum; Martin Stiftinger - Web page: https://patentgrep.com/patent/US9040375B2 ## CPC - H10B 41/50: characterised by the boundary region between the core region and the peripheral circuit region - H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 41/35: with a cell select transistor, e.g. NAND - H10B 41/41: of a memory region comprising a cell select transistor, e.g. NAND - H10B 41/43: comprising only one type of peripheral transistor - H10D 30/0411: {of FETs having floating gates} - H10D 30/0413: {of FETs having charge-trapping gate insulators, e.g. MNOS transistors} - H10D 30/6891: {characterised by the shapes, relative sizes or dispositions of the floating gate electrode} - H10D 30/694: {characterised by the shapes, relative sizes or dispositions of the gate electrodes} - H10D 64/035: {comprising conductor-insulator-conductor-insulator-semiconductor structures} - H10D 64/037: {comprising charge-trapping insulators} - H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs} - H10W 20/0698: {Local interconnections} - H10B: ELECTRONIC MEMORY DEVICES - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A method for processing a carrier accordance with various embodiments may include: forming a structure over the carrier, the structure including at least two adjacent structure elements arranged at a first distance between the same; depositing a spacer layer over the structure, wherein the spacer layer may be deposited having a thickness greater than half of the first distance, wherein the spacer layer may include electrically conductive spacer material; removing a portion of the spacer layer, wherein spacer material of the spacer layer may remain in a region between the at least two adjacent structure elements; and electrically contacting the remaining spacer material. ## Claims ### Claim 1 A method for processing a carrier, the method comprising: forming a structure over the carrier, the structure comprising two adjacent structure elements respectively formed in a U-shape so that the two adjacent structure elements are arranged at a first distance between the same; depositing a spacer layer over the structure, wherein the spacer layer is deposited having a thickness greater than half of the first distance, wherein the spacer layer comprises electrically conductive spacer material; removing a portion of the spacer layer, wherein spacer material of the spacer layer remains between the two adjacent structure elements and electrically contacts the two adjacent structure elements; and electrically contacting the remaining spacer material. ### Claim 2 (depends on 1) The method of claim 1, wherein each of the two adjacent structure elements is forming at least a part of a metal-oxide-semiconductor field-effect transistor. ### Claim 3 (depends on 2) The method of claim 2, wherein each of the two adjacent structure elements is forming a part of a gate of a metal-oxide-semiconductor field-effect transistor. ### Claim 4 (depends on 3) The method of claim 3, wherein each of the two adjacent structure elements comprises a floating gate of a metal-oxide-semiconductor field-effect transistor. ### Claim 5 (depends on 1) The method of claim 1, wherein each of the two adjacent structure elements comprises at least one of a floating gate and a control gate of a floating gate metal-oxide-semiconductor field-effect transistor. ### Claim 6 (depends on 1) The method of claim 1, wherein the spacer material comprises polycrystalline silicon. ### Claim 7 (depends on 1) The method of claim 1, wherein the spacer layer is deposited having a thickness of less than or equal to about 200 nm. ### Claim 8 (depends on 1) The method of claim 1, wherein removing part of the spacer layer comprises exposing a surface of each of the two adjacent structure elements while spacer material remains at least partially at the sidewalls of each of the two adjacent structure elements. ### Claim 9 (depends on 8) The method of claim 8, wherein the remaining spacer material at the sidewalls of each of the two adjacent structure elements provide a control line of a field-effect transistor. ### Claim 10 (depends on 1) The method of claim 1, wherein the electrically contacting the remaining spacer material comprises: depositing a masking material over the spacer layer; removing the masking material to partially expose the remaining spacer material between the two adjacent structure elements; and depositing electrically conductive material contacting the remaining spacer material between the two adjacent structure elements. ### Claim 11 A method for processing a chip, the method comprising: forming a structure over a substrate, wherein the structure comprises at least one structure element, wherein each of the at least one structure element comprises at least two adjacent sidewalls facing each other arranged at a first distance between the at least two adjacent sidewalls; depositing a spacer layer over the structure covering each of the at least one structure element, wherein the spacer layer is deposited having a spacer layer thickness greater than half of the first distance between the at least two adjacent sidewalls; partially removing the spacer layer, wherein spacer material of the spacer layer remains in at least one region between the at least two adjacent sidewalls of each of the at least one structure element; and electrically contacting the remaining spacer material. ### Claim 12 (depends on 11) The method of claim 11, wherein the electrically contacting the remaining spacer material comprises: depositing a masking material over at least part of the spacer layer; removing the masking material to partially expose the remaining spacer material between the at least two adjacent sidewalls of the at least one structure element; and depositing electrically conductive material contacting the remaining spacer material between the at least two adjacent sidewalls of the at least one structure element. ### Claim 13 A method for processing a chip, the method comprising: forming a structure over a substrate, wherein the structure comprises two structure elements, wherein each of the two structure elements comprises at least two adjacent sidewalls facing each other so that a third sidewall is provided for each of the two structure elements, wherein the two third sidewalls of the two structure elements are facing each other and are arranged at a first distance between each other; depositing a spacer layer over the structure covering the two structure elements, wherein the spacer layer is deposited having a spacer layer thickness greater than half of the first distance between the two third sidewalls of the two structure elements; partially removing the spacer layer, wherein spacer material of the spacer layer remains between the two third sidewalls of the two structure elements; and electrically contacting the remaining spacer material. ### Claim 14 (depends on 13) The method of claim 13, wherein each of the two structure elements comprises at least one of a floating gate and a control gate of a floating gate metal-oxide-semiconductor field-effect transistor. ### Claim 15 (depends on 13) The method of claim 13, wherein the spacer material comprises electrically conductive material. ### Claim 16 (depends on 13) The method of claim 13, wherein the spacer material comprises polycrystalline silicon. ### Claim 17 (depends on 14) The method of claim 14, wherein the remaining spacer material between the two third sidewalls of the two structure elements provide a single control line for the two floating gate metal-oxide-semiconductor field-effect transistors.