# US 9,040,374 B2 · Semiconductor device and method of manufacturing the same

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- Number: US 9,040,374 B2
- Document ID: US9040374B2
- Status: Granted
- Kind: B2
- Application number: 13/830,727
- Filed: 2013-03-14
- Published: 2014-06-19
- Granted: 2015-05-26
- Earliest claimed: 2012-12-13
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Dong Kee Lee
- Web page: https://patentgrep.com/patent/US9040374B2

## CPC

- H10D 1/47: Resistors having no potential barriers
- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 41/42: Simultaneous manufacture of periphery and memory cells
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/35: with cell select transistors, e.g. NAND
- H10B 43/40: characterised by the peripheral circuit region
- H10B 63/30: {comprising selection components having three or more electrodes, e.g. transistors}
- H10D 84/811: {Combinations of field-effect devices and one or more diodes, capacitors or resistors}
- H10D 84/817: {Combinations of field-effect devices and resistors only}
- H10N 70/25: {based on bulk electronic defects, e.g. trapping of electrons}
- H10N 70/821: {Device geometry}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/3456: {Polycrystalline}
- H10P 50/264: {by chemical means}
- H10P 50/283: {by chemical means}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10N 70/883: {Oxides or nitrides}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Disclosed is a semiconductor device having a substrate including first and second regions. First interlayer insulation layers and conductive patterns alternately are stacked on a first region of the substrate. A second interlayer insulation layer covers the first interlayer insulation layers and the conductive patterns. A resistor is formed in the second interlayer insulation layer in the second region of the substrate.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate including first and second regions;
first interlayer insulation layers and conductive patterns alternately stacked in the first region of the substrate;
a through hole passing through the first interlayer insulation layers and the conductive patterns;
a channel layer formed in the through hole;
a second interlayer insulation layer covering the first interlayer insulation layers and the conductive patterns; and
a resistor formed in the second interlayer insulation layer in the second region of the substrate.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, further comprising:
an insulation layer formed in a central portion of the channel layer, wherein a height of the insulation layer is less than a height of the channel layer; and
a conductive plug formed in the central portion of the channel layer and over the insulation layer,
wherein the channel layer is formed along a surface of the through hole,
wherein the channel layer has a tubular shape,
wherein the central portion of the channel layer is filled with the insulation layer and the conductive plug.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein the conductive plug is formed of the same material as that of the resistor.

### Claim 4 (depends on 2)

The semiconductor device of claim 2, wherein the conductive plug and the resistor have a same height.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein edges of the conductive patterns and edges of the first interlayer insulation layers extend from the first region to the second region so that a stepwise structure is formed on the second region of the substrate.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, further comprising:
a driving gate formed in the second region of the substrate, wherein the driving gate is covered by the second interlayer insulation layer, and is disposed adjacent to the stepwise structure,
wherein the resistor includes a first resistor overlapping the driving gate.

### Claim 7 (depends on 5)

The semiconductor device of claim 5, wherein the resistor includes a second resistor disposed in the second interlayer insulation layer covering the stepwise structure.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein the resistor is formed of a polysilicon.

### Claim 9

A semiconductor device, comprising:
a substrate including first and second regions;
first interlayer insulation layers and conductive patterns alternately stacked in the first region of the substrate;
a through hole passing through the first interlayer insulation layers and the conductive patterns;
a channel layer formed in the through hole;
a second interlayer insulation layer covering the first interlayer insulation layers and the conductive patterns; and
a resistor formed in the second interlayer insulation layer in the second region of the substrate,
wherein edges of the conductive patterns and edges of the first interlayer insulation layers extend from the first region to the second region so that a stepwise structure is formed in the second region of the substrate.