# US 9,040,373 B2 · Silicon device on SI:C-OI and SGOI and method of manufacture

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- Number: US 9,040,373 B2
- Document ID: US9040373B2
- Status: Granted
- Kind: B2
- Application number: 14/105,899
- Filed: 2013-12-13
- Published: 2014-04-17
- Granted: 2015-05-26
- Earliest claimed: 2003-11-19
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Dureseti Chidambarrao; Omer H. Dokumaci; Oleg Gluschenkov
- Web page: https://patentgrep.com/patent/US9040373B2

## CPC

- H10D 62/8325: {Silicon carbide}
- H10D 10/891: {comprising lattice-mismatched active layers, e.g. SiGe strained-layer transistors}
- H10D 30/0278: {forming single crystalline channels on wafers after forming insulating device isolations}
- H10D 30/751: {having composition variations in the channel regions}
- H10D 30/792: {comprising applied insulating layers, e.g. stress liners}
- H10D 30/795: {being in lateral device isolation regions, e.g. STI}
- H10D 30/798: {being provided in or under the channel regions}
- H10D 30/832: {Thin-film junction FETs [JFET]}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 84/0128: {Manufacturing their channels}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/035: {using silicon carbide [SiC] technology}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 86/01: Manufacture or treatment
- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor structure and method of manufacturing is provided. The method of manufacturing includes forming shallow trench isolation (STI) in a substrate and providing a first material and a second material on the substrate. The first material and the second material are mixed into the substrate by a thermal anneal process to form a first island and second island at an nFET region and a pFET region, respectively. A layer of different material is formed on the first island and the second island. The STI relaxes and facilitates the relaxation of the first island and the second island. The first material may be deposited or grown Ge material and the second material may deposited or grown Si:C or C. A strained Si layer is formed on at least one of the first island and the second island.

## Claims

### Claim 1

A semiconductor structure, comprising:
a substrate;
a shallow trench isolation (STI) in the substrate;
a first island of mixed material and a second island of mixed material in the substrate, wherein the first island and the second island have a different relaxed crystal lattice with different dimensions between atoms; and
a first Si layer on the first island and a second Si layer on the second island,
wherein the STI is high temperature stable amorphous material.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1, wherein the first Si layer is strained and the second Si layer is strained.

### Claim 3 (depends on 1)

The semiconductor structure of claim 1, wherein the STI comprises a material that has a lower viscosity as the temperature rises.

### Claim 4 (depends on 1)

The semiconductor structure of claim 1, wherein the first island has a lattice constant a≧aSi and the second island has a lattice constant a≦aSi.

### Claim 5 (depends on 1)

The semiconductor structure of claim 1, wherein:
the first island comprises SiGe and contacts the STI; and
the second island comprises Si:C and contacts the STI.

### Claim 6 (depends on 5)

The semiconductor structure of claim 5, wherein:
the first Si island is tensile strained; and
the second Si island is compressive strained.

### Claim 7

A semiconductor structure, comprising:
a substrate;
a shallow trench isolation (STI) in the substrate;
a first island of mixed material and a second island of mixed material in the substrate. wherein the first island and the second island have a different relaxed crystal lattice with different dimensions between atoms; and
a first Si layer on the first island and a second Si layer on the second island,
wherein one of the first Si layer and the second Si layer is tensile strained, and another one of the first Si layer and the second Si layer is compressively strained, respectively.

### Claim 8

A semiconductor structure, comprising:
a substrate;
a shallow trench isolation (STI) in the substrate;
a first island of SiGe in the substrate and contacting the STI;
a second island of Si:C in the substrate and contacting the STI;
a first strained Si layer on the first island; and
a second strained Si layer on the second island.

### Claim 9 (depends on 8)

The semiconductor structure of claim 8, wherein the first island and the second island have a different relaxed crystal lattice with different dimensions between atoms.

### Claim 10 (depends on 8)

The semiconductor structure of claim 8, wherein the STI is high temperature stable amorphous material.

### Claim 11 (depends on 8)

The semiconductor structure of claim 8, wherein the STI comprises a material that has a lower viscosity as the temperature rises.

### Claim 12 (depends on 8)

The semiconductor structure of claim 8, wherein the first island has a lattice constant a≧aSi and the second island has a lattice constant a≦aSi.

### Claim 13 (depends on 8)

The semiconductor structure of claim 8, wherein:
the first Si island is tensile strained; and
the second Si island is compressive strained.