# US 9,040,367 B2 · Latch-up immunity nLDMOS

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- Number: US 9,040,367 B2
- Document ID: US9040367B2
- Status: Granted
- Kind: B2
- Application number: 13/590,561
- Filed: 2012-08-21
- Published: 2014-02-27
- Granted: 2015-05-26
- Earliest claimed: 2012-08-21
- Assignees: Globalfoundries Singapore Pte. Ltd.
- Applicants: Da-Wei Lai
- Inventors: Da-Wei Lai
- Web page: https://patentgrep.com/patent/US9040367B2

## CPC

- H10D 89/813: {specially adapted to provide an electrical current path other than the field-effect induced current path}
- H10D 30/0281: {of lateral DMOS [LDMOS] FETs}
- H10D 30/64: Double-diffused metal-oxide semiconductor [DMOS] FETs
- H10D 30/65: Lateral DMOS [LDMOS] FETs
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/157: {Impurity concentrations or distributions}
- H10D 64/258: {characterised by the relative positions of the source or drain electrodes with respect to the gate electrode}
- H10D 64/529: {Electrodes for IGFETs contacting substrate regions, e.g. for grounding or preventing parasitic effects}
- H10D 64/663: {the additional layers comprising a silicide layer contacting the layer of silicon, e.g. polycide gates}
- H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs}
- H10D 62/378: {Contact regions to the substrate regions}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

An improved nLDMOS ESD protection device having an increased holding voltage is disclosed. Embodiments include: providing in a substrate a DVNW region; providing a HVPW region in the DVNW region; providing bulk and source regions in the HVPW region; providing a drain region in the DVNW region, separate from the HVPW region; and providing a polysilicon gate over a portion of the HVPW region and the DVNW region.

## Claims

### Claim 1

A method comprising:
providing in a substrate a dual voltage n-well (DVNW) region;
providing a high voltage p-well (HVPW) region in the DVNW region;
providing bulk and source regions in the HVPW region;
providing a drain region in the DVNW region, separate from the HVPW region;
providing a polysilicon gate over a portion of the HVPW region and the DVNW region; and
providing in the source region in the HVPW region, second and third N+ regions and a first P+ region, the second and third N+ regions being separated by the first P+ region.

### Claim 2 (depends on 1)

The method according to claim 1, comprising:
providing in the DVNW region in the drain region an n-well (NW) region.

### Claim 3 (depends on 2)

The method according to claim 2, comprising:
providing a first N+ region in the NW region.

### Claim 4 (depends on 3)

The method according to claim 3, comprising:
forming a silicided block layer on the first N+ region, a portion of the polysilicon gate, and the DVNW therebetween.

### Claim 5 (depends on 1)

The method according to claim 1, comprising:
coupling the second and third N+ regions and the polysilicon gate to a ground rail; and
coupling the first N+ region to an I/O pad.

### Claim 6 (depends on 5)

The method according to claim 5, further comprising:
providing a second P+ region in the substrate, separate from the DVNW region; and
coupling the second P+ region to the ground rail.

### Claim 7 (depends on 6)

The method according to claim 6, comprising:
providing an ESD current path from the I/O pad to the ground rail through the NW, DVNW, HVPW, and third N+ regions during an ESD event.

### Claim 8 (depends on 1)

The method according to claim 1, wherein the first P+ region and the second N+ region abut each other, having no other element therebetween.