# US 9,040,365 B2 · Method for fabricating thin film transistor array substrate

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- Number: US 9,040,365 B2
- Document ID: US9040365B2
- Status: Granted
- Kind: B2
- Application number: 13/622,913
- Filed: 2012-09-19
- Published: 2013-03-21
- Granted: 2015-05-26
- Earliest claimed: 2011-09-19
- Assignees: LG Display Co., Ltd.
- Applicants: LG Display Co., Ltd.
- Inventors: JungSun Beak; Jeong Oh Kim; Jong Won Lee
- Web page: https://patentgrep.com/patent/US9040365B2

## CPC

- H10D 86/0231: {using masks, e.g. half-tone masks}
- G02F 1/136227: {Through-hole connection of the pixel electrode to the active element through an insulation layer}
- H10D 30/0316: {of lateral bottom-gate TFTs comprising only a single gate}
- H10D 30/0321: {comprising silicon, e.g. amorphous silicon or polysilicon}
- H10D 86/441: {Interconnections, e.g. scanning lines}
- H10D 86/60: wherein the TFTs are in active matrices
- H10P 50/71: {using masks for conductive or resistive materials}
- G02F 1/134318: {having a patterned common electrode}
- G02F 1/134372: {for fringe field switching [FFS] where the common electrode is not patterned}
- G02F 1/136286: {Wiring, e.g. gate line, drain line}
- H10D 30/6732: {Bottom-gate only TFTs}
- H10D 30/6746: {Amorphous silicon}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method of fabricating a thin film transistor array substrate is disclosed. The method includes: sequentially forming a first passivation layer, a photo acryl layer and a first transparent metal layer on the substrate provided with the source/drain electrodes and so on; forming a common electrode, which is disposed in the pixel region, and first through third contact holes, which are positioned in regions of the drain electrode, the gate pad and the data pad, respectively, using one of a half-tone mask and a diffractive mask; forming a second passivation layer on the substrate provided with the first through third contact holes; exposing the drain electrode, the gate pad and the data pad by removing the first and second passivation layers from the drain electrode region, the gate pad region and data pad region; and forming a pixel electrode on the second passivation layer opposite to the common electrode by forming a second transparent metal layer on the substrate and performing a third mask procedure for the second transparent metal layer.

## Claims

### Claim 1

A method of fabricating a thin film transistor array substrate, the method comprising:
preparing a substrate defined into a display area and a non-display area;
forming a gate electrode and a gate line, which are disposed in the display area, and a gate pad and a data pad, which are disposed in the non-display area, by forming a metal film on the substrate and performing a first mask procedure for the metal film;
sequentially forming a gate insulation film and a channel layer on the substrate provided with the gate electrode;
forming source/drain electrodes and a data line by forming a source/drain metal film on the substrate provided with the channel layer and performing a second mask procedure for the source/drain metal film;
sequentially forming a first passivation layer, a photo acryl layer and a first transparent metal layer on the substrate provided with the source/drain electrodes;
forming a common electrode, which is disposed in the pixel region, and first through third contact holes, which are positioned in regions of the drain electrode, the gate pad and the data pad, respectively, using one of a half-tone mask and a diffractive mask;
forming a second passivation layer on the substrate provided with the first through third contact holes;
exposing the drain electrode, the gate pad and the data pad by removing the first and second passivation layers from the drain electrode region, the gate pad region and data pad region; and
forming a pixel electrode on the second passivation layer opposite to the common electrode by forming a second transparent metal layer on the substrate and performing a third mask procedure for the second transparent metal layer.

### Claim 2 (depends on 1)

The method of claim 1, wherein the formation of the common electrode and the first through third contact holes includes:
forming a first photo resist pattern on the first transparent metal layer;
forming the first through third contact holes by removing the photo acryl layer from the drain electrode region, the gate pad region and the data pad region using wet and dry etching processes;
forming a second photo resist pattern by performing an ashing process for the substrate provided with the first through third contact holes; and
forming the common electrode on the photo acryl layer by wet etching the first transparent metal layer using the second photo resist pattern as an etch mask.

### Claim 3 (depends on 1)

The method of claim 1, wherein the first passivation layer on the drain electrode, the gate pad and the data pad remains after the formation of the first through third contact holes.

### Claim 4 (depends on 1)

The method of claim 1, wherein the photo acryl layer is formed from an organic material.

### Claim 5 (depends on 1)

The method of claim 1, wherein the photo acryl layer has a lower dielectric constant than that of the first passivation layer.

### Claim 6 (depends on 5)

The method of claim 5, wherein the dielectric constant of the photo acryl layer is in a range of about 3.4˜about 3.8.

### Claim 7 (depends on 5)

The method of claim 5, wherein the first passivation layer is formed in a thickness of about 1000 Å.

### Claim 8

A method of fabricating a thin film transistor array substrate, the method comprising:
preparing a substrate defined into a display area and a non-display area;
forming a gate electrode and a gate line, which are disposed in the display area, and a gate pad and a data pad, which are disposed in the non-display area, by forming a metal film on the substrate and performing a first mask procedure for the metal film;
forming source/drain electrodes and a data line by forming a gate insulation film, a semiconductor layer and a source/drain metal film on the substrate provided with the gate electrode and performing form the semiconductor layer and the source/drain metal film a second mask procedure which uses one of a first half-tone and a first diffractive mask;
sequentially forming a first passivation layer, a photo acryl layer and a first transparent metal layer on the substrate provided with the source/drain electrodes;
forming a common electrode, which is disposed in the pixel region, and first through third contact holes, which are positioned in regions of the drain electrode, the gate pad and the data pad, respectively, using one of a half-tone mask and a diffractive mask;
forming a second passivation layer on the substrate provided with the first through third contact holes;
exposing the drain electrode, the gate pad and the data pad by removing the first and second passivation layers from the drain electrode region, the gate pad region and data pad region; and
forming a pixel electrode on the second passivation layer opposite to the common electrode by forming a second transparent metal layer on the substrate and performing a third mask procedure for the second transparent metal layer.

### Claim 9 (depends on 8)

The method of claim 8, wherein the formation of the common electrode and the first through third contact holes includes: forming a first photo resist pattern on the first transparent metal layer; forming the first through third contact holes by removing the photo acryl layer from the drain electrode region, the gate pad region and the data pad region using wet and dry etching processes; forming a second photo resist pattern by performing an ashing process for the substrate provided with the first through third contact holes; and forming the common electrode on the photo acryl layer by wet etching the first transparent metal layer using the second photo resist pattern as an etch mask.

### Claim 10 (depends on 8)

The method of claim 8, wherein the first passivation layer on the drain electrode, the gate pad and the data pad remains after the formation of the first through third contact holes.

### Claim 11 (depends on 8)

The method of claim 8, wherein the photo acryl layer is formed from an organic material.

### Claim 12 (depends on 8)

The method of claim 8, wherein the photo acryl layer has a lower dielectric constant than that of the first passivation layer.

### Claim 13 (depends on 12)

The method of claim 12, wherein the dielectric constant of the photo acryl layer is in a range of about 3.4-about 3.8.

### Claim 14 (depends on 12)

The method of claim 12, wherein the first passivation layer is formed in a thickness of about 1000 Å.