Chip scale package with electronic component received in encapsulant, and fabrication method thereof

A chip scale package, comprising:

• a copper clad laminate (CCL) hard board having a first surface and an opposite second surface, wherein a first wiring layer and a second wiring layer are respectively only formed on the first surface and the second surface and are electrically connected to each other, and the first wiring layer has a plurality of conductive pads;
• a plurality of conductive elements disposed on at least a portion of the conductive pads;
• an electronic component having an active surface with a plurality of electrode pads thereon and an inactive surface opposite to the active surface and being mounted on the first surface of the hard board via the inactive surface thereof;
• a single encapsulating layer formed on the first surface of the hard board for encapsulating the conductive elements and the electronic component, the active surface of the electronic component and surfaces of the conductive elements being exposed from the encapsulating layer, wherein the active surface of the electronic component is flush with a surface of the encapsulating layer;
• a first dielectric layer formed on the encapsulating layer and having a plurality of openings for exposing the electrode pads on the active surface of the electronic component and the surfaces of the conductive elements;
• and
• a single third wiring layer formed on the first dielectric layer so as to be in contact with and electrically connected to the conductive elements and the electrode pads.