# US 9,040,358 B2 · Semiconductor device and method for manufacturing the same

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- Number: US 9,040,358 B2
- Document ID: US9040358B2
- Status: Granted
- Kind: B2
- Application number: 14/467,930
- Filed: 2014-08-25
- Published: 2014-12-11
- Granted: 2015-05-26
- Earliest claimed: 2009-11-05
- Assignees: Renesas Electronics Corporation
- Applicants: Renesas Electronics Corporation
- Inventors: Kazuya Fukuhara; Kiyonori Yoshitomi; Takehiko Ikegami; Yujiro Kawasoe
- Web page: https://patentgrep.com/patent/US9040358B2

## CPC

- H10W 70/465: {Bumps or wires}
- H10W 70/411: {Chip-supporting parts, e.g. die pads}
- H10W 70/421: {Shapes or dispositions}
- H10W 70/458: {of insulating layers on leadframes}
- H10W 72/90: Bond pads, in general
- H10W 74/01: Manufacture or treatment
- H10W 90/811: {Multiple chips on leadframes}
- H10W 72/07141: {Means for applying energy, e.g. ovens or lasers}
- H10W 72/073: {of die-attach connectors}
- H10W 72/075: {of bond wires}
- H10W 72/07521: {Aligning}
- H10W 72/07552: {changes in structures or sizes}
- H10W 72/07553: {changes in shapes}
- H10W 72/07554: {changes in dispositions}
- H10W 72/527: {Multiple bond wires having different sizes}
- H10W 72/531: {Shapes of wire connectors}
- H10W 72/536: {the connected ends being ball-shaped}
- H10W 72/5363: {the connected ends being wedge-shaped}
- H10W 72/5366: {the bond wires having kinks}
- H10W 72/537: {Multiple bond wires having different shapes}
- H10W 72/5449: {not being orthogonal to a side surface of the chip, e.g. fan-out arrangements}
- H10W 72/5473: {multiple bond wires connected to a common bond pad}
- H10W 72/5522: {comprising gold [Au]}
- H10W 72/5525: {comprising copper [Cu]}
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/932: {Plan-view shape, i.e. in top view}
- H10W 72/934: {Cross-sectional shape, i.e. in side view}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/111: {the semiconductor body being completely enclosed}
- H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device permitting the reduction of cost is disclosed. In a semiconductor package wherein electrode pads of a semiconductor chip and corresponding inner leads are electrically coupled with each other through a plurality of bonding wires, sensing wires (second and fourth bonding wires) are made thinner than other bonding wires (first and third bonding wires) coupled to inner leads same as those with the sensing wires coupled thereto, thereby reducing the cost of gold wires to attain the reduction in cost of the semiconductor package.

## Claims

### Claim 1

A method of manufacturing a semiconductor device, comprising the steps of:
(a) providing a lead frame including a chip mounting area and a plurality of leads;
(b) mounting a semiconductor chip over the chip mounting area of the lead frame, the semiconductor chip having a plurality of electrode pads;
(c) coupling the leads and the electrode pads of the semiconductor chip via a plurality of bonding wires; and
(d) sealing the semiconductor chip, the bonding wires and a portion of each of the leads with a resin,
wherein the bonding wires include a first bonding wire coupling a first lead of the leads with a first electrode pad of the electrode pads, and a second bonding wire coupling the first lead with a second electrode pad of the electrode pads;
wherein a diameter of the second bonding wire is smaller than that of the first boding wire; and
wherein, in the step (d), the resin is supplied from the first bonding wire side than the second bonding wire side toward the second bonding wire side.

### Claim 2 (depends on 1)

The method according to claim 1,
wherein, in the step (d), the lead frame over which the semiconductor chip is mounted is arranged between a first die and a second die such that both the semiconductor chip and the bonding wires are arranged inside of a cavity of the first die; and
wherein, in the step (d), the resin is supplied into the cavity.

### Claim 3 (depends on 2)

The method according to claim 2,
wherein, a loop height of the second bonding wire is larger than that of the first bonding wire.

### Claim 4 (depends on 2)

The method according to claim 2,
wherein, a part of the second bonding wire is located further from the semiconductor chip than a part of the first bonding wire, in a direction of a thickness of the semiconductor chip.

### Claim 5 (depends on 3)

The method according to claim 3,
wherein, in plan view, a part of the first lead with which the second bonding wire is coupled is located further from an outer periphery portion of the semiconductor chip than a part of the first lead with which the first bonding wire is coupled.

### Claim 6

A method of manufacturing a semiconductor device, comprising the steps of:
(a) providing a lead frame including a chip mounting area and a plurality of leads;
(b) mounting a semiconductor chip over the chip mounting area of the lead frame, the semiconductor chip having a plurality of electrode pads;
(c) coupling the leads and the electrode pads of the semiconductor chip via a plurality of bonding wires; and
(d) arranging the semiconductor chip and the boding wires inside of a cavity of a molding die, and sealing the semiconductor chip, the bonding wires and a portion of each of the leads with a resin by supplying the resin into the cavity of the molding die via a gate of the molding die,
wherein the bonding wires include a first bonding wire coupling a first lead of the leads with a first electrode pad of the electrode pads, and a second bonding wire coupling the first lead with a second electrode pad of the electrode pads;
wherein a diameter of the second bonding wire is smaller than that of the first boding wire; and
wherein, in the step (d), the second bonding wire is located further from the gate of the molding die than the first bonding wire.

### Claim 7 (depends on 6)

The method according to claim 6,
wherein the first bonding wire includes a first end portion coupling with the first electrode pad,
wherein the second bonding wire includes a second end portion coupling with the second electrode pad; and
wherein, in the step(d), the second end portion of the second bonding wire is located further from the gate of the molding die than the first end portion of the first bonding wire.

### Claim 8 (depends on 7)

The method according to claim 7,
wherein the first bonding wire includes a third end portion coupling with the first lead,
wherein the second bonding wire includes a fourth end portion coupling with the first lead; and
wherein, in the step (d), the fourth end portion of the second bonding wire is located further from the gate of the molding die than the third end portion of the first bonding wire.

### Claim 9 (depends on 7)

The method according to claim 7,
wherein, in the step (c), the first bonding wire is formed by a ball bonding method which forms a first ball-like electrode,
wherein, in the step (c), the second bonding wire is formed by a ball bonding method which forms a second ball-like electrode,
wherein the first end portion of the first bonding wire is the first ball-like electrode; and
wherein the second end portion of the second bonding wire is the second ball-like electrode.

### Claim 10 (depends on 8)

The method according to claim 8,
wherein, a loop height of the second bonding wire is larger than that of the first bonding wire.

### Claim 11 (depends on 8)

The method according to claim 8,
wherein, a part of the second bonding wire is located further from the semiconductor chip than a part of the first bonding wire, in a direction of a thickness of the semiconductor chip.

### Claim 12 (depends on 10)

The method according to claim 10,
wherein, in plan view, a part of the first lead with which the second bonding wire is coupled is located further from an outer periphery portion of the semiconductor chip than a part of the first lead with which the first bonding wire is coupled.