# US 9,040,357 B2 · Semiconductor packaging method using connecting plate for internal connection

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- Number: US 9,040,357 B2
- Document ID: US9040357B2
- Status: Granted
- Kind: B2
- Application number: 14/083,277
- Filed: 2013-11-18
- Published: 2014-03-20
- Granted: 2015-05-26
- Earliest claimed: 2010-03-12
- Assignees: Alpha and Omega Semiconductor Incorporated
- Applicants: Alpha and Omega Semiconductor Incorporated
- Inventors: Jun Lu; Kai Liu; Yan Xun Xue
- Web page: https://patentgrep.com/patent/US9040357B2

## CPC

- H10W 74/016: {using moulds}
- H10W 70/427: {Bent parts}
- H10W 70/464: {Additional interconnections in combination with leadframes}
- H10W 70/466: {Tape carriers or flat leads}
- H10W 70/481: {for devices being provided for in groups H10D8/00 - H10D48/00}
- H10W 72/60: Strap connectors, e.g. thick copper clips for grounding of power devices
- H10W 90/00: Package configurations
- H10W 90/811: {Multiple chips on leadframes}
- H10W 72/07337: {using a polymer adhesive, e.g. an adhesive based on silicone or epoxy}
- H10W 72/07636: {Soldering or alloying}
- H10W 72/07653: {changes in shapes}
- H10W 72/631: {Shapes of strap connectors}
- H10W 72/652: {comprising metals or metalloids, e.g. silver}
- H10W 72/871: {Bond wires and strap connectors}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/886: {Die-attach connectors and strap connectors}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/111: {the semiconductor body being completely enclosed}
- H10W 74/127: {characterised by arrangements for sealing or adhesion}
- H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W 90/763: {between laterally-adjacent chips}
- H10W 90/766: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor package with connecting plate for internal connection comprise: a plurality of chips each having a plurality of contact areas on a top surface; one or more connecting plates having a plurality of electrically isolated connecting plate portions each connecting a contact area of the semiconductor chips. The method of making the semiconductor package includes the steps of connecting one or more connecting plates to a plurality of semiconductor chips, applying a molding material to encapsulate the chips and the connecting plates, separating a plurality of connecting plate portions of the connecting plates by shallow cutting through or by grinding.

## Claims

### Claim 1

A process of making a semiconductor package comprising:
a. providing a plurality of semiconductor chips each having a plurality of electrode contact areas disposed on a top surface;
b. providing a first connecting plate comprising a plurality of connecting plate tie bar upward regions separating the connecting plate into a plurality of connecting plate portions;
c. electrically connecting each of the plurality of connecting plate portions to a contact area of the plurality of electrode contact areas;
d. applying a molding compound to substantially encapsulate the plurality of semiconductor chips and the first connecting plate; and
e. grinding a top surface of the molding compound and the plurality of tie bar upward regions to the extent a conductive section of each of the plurality of tie bar upward regions is removed such that each of the plurality of tie bar upward regions is electrically isolating from the other.

### Claim 2 (depends on 1)

The process of making a semiconductor package of claim 1 further comprising:
applying a dielectric layer on top of the grinded surface.