# US 9,040,354 B2 · Chip comprising a fill structure > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,040,354 B2 - Document ID: US9040354B2 - Status: Granted - Kind: B2 - Application number: 14/184,856 - Filed: 2014-02-20 - Published: 2014-06-19 - Granted: 2015-05-26 - Earliest claimed: 2011-09-28 - Assignees: Infineon Technologies AG - Applicants: Infineon Technologies AG - Inventors: Gunther Mackh; Gerhard Leschik; Adolf Koller; Harald Seidl - Web page: https://patentgrep.com/patent/US9040354B2 ## CPC - H10P 54/00: Cutting or separating of wafers, substrates or parts of devices - H10W 42/00: Arrangements for protection of devices (arrangements for thermal protection H10W40/00) - G06F 30/39: Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) - H10D 84/01: Manufacture or treatment - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A chip includes a dielectric layer and a fill structure in the dielectric layer, wherein the fill structure extends along a dicing edge of the chip, with the fill structure abutting the dicing edge. ## Claims ### Claim 1 A method of manufacturing a plurality of chips, the method comprising: forming a dielectric layer over a substrate comprising dicing lines for singulating the substrate; forming a fill structure having a periodic structure in the dielectric layer, wherein the fill structure is disposed between regions of the substrate comprising the plurality of chips, wherein the periodic structure has a first periodicity with a first periodic pitch in a first lateral direction and having a second periodicity with a second periodic pitch in a second lateral direction perpendicular to the first lateral direction, and wherein a width of each of the dicing lines is less than 100 μm, and wherein the first periodic pitch is less than 20 μm; and singulating the substrate through the dicing lines to form the plurality of chips. ### Claim 2 (depends on 1) The method for manufacturing according to claim 1, and wherein a chip area of each of the plurality of chips is less than 10 mm2. ### Claim 3 (depends on 1) The method for manufacturing according to claim 1, wherein the first periodic pitch is less than 5 μm. ### Claim 4 (depends on 1) The method for manufacturing according to claim 1, wherein a width of each of the dicing lines is less than 25 μm. ### Claim 5 (depends on 1) The method for manufacturing according to claim 1, wherein the first periodic pitch is the same as the second periodic pitch. ### Claim 6 (depends on 1) The method for manufacturing according to claim 1, wherein the singulating of the substrate is performed by using stealth dicing. ### Claim 7 (depends on 1) The method for manufacturing according to claim 1, wherein the fill structure comprises metal, oxide and/or polysilicon layers. ### Claim 8 (depends on 1) The method for manufacturing according to claim 1, wherein the fill structure comprises a density of metal, oxide, or polysilicon of at least 10%. ### Claim 9 (depends on 1) The method for manufacturing according to claim 1, wherein the fill structure comprises a density of metal, oxide, or polysilicon of at least 50%. ### Claim 10 (depends on 1) The method for manufacturing according to claim 1, wherein the fill structure comprises at least 25% metal. ### Claim 11 (depends on 1) The method for manufacturing according to claim 1, wherein the periodic structure is formed by a grid of metal vias or metal conductor line fragments. ### Claim 12 (depends on 1) The method for manufacturing according to claim 1, wherein the chip comprises a sealing ring which extends in parallel to the dicing lines. ### Claim 13 (depends on 1) The method for manufacturing according to claim 1, wherein the dielectric layer has a dielectric constant smaller than 3.9. ### Claim 14 (depends on 1) The method for manufacturing according to claim 1, wherein average half-pitch of the chip is smaller than 65 nm. ### Claim 15 (depends on 1) The method for manufacturing according to claim 1, wherein the singulating cuts through the periodic structure. ### Claim 16 A method for manufacturing a plurality of chips, the method comprising: providing a wafer comprising a dielectric layer, wherein the wafer comprises a fill structure of the dielectric layer within a dicing line, wherein the fill structure forms a periodic structure, and a plurality of chip areas separated by at least the dicing line, wherein the periodic structure comprises a first periodicity with a first periodic pitch in a first lateral direction and a second periodicity with a second periodic pitch in a second lateral direction perpendicular to the first lateral direction, wherein the first periodic pitch is a different pitch from the second periodic pitch, and wherein the first periodic pitch and the second periodic pitch are both smaller than 5 μm; and singulating the plurality of chips along the dicing line. ### Claim 17 (depends on 6) The method for manufacturing according to claim 6, wherein the step of singulating the plurality of chips is performed by using stealth dicing. ### Claim 18 (depends on 16) The method for manufacturing according to claim 16, wherein a width of each of the dicing lines is less than 100 μm. ### Claim 19 (depends on 16) The method for manufacturing according to claim 16, wherein the singulating cuts through the periodic structure. ### Claim 20 A method for manufacturing a plurality of chips, the method comprising: forming a plurality of chip areas separated by at least a dicing line within a wafer; forming a dielectric layer over the wafer; and forming a fill structure within the dicing line in the dielectric layer, wherein the fill structure forms a periodic structure extending in a lateral dimension parallel and perpendicular to the dicing line, and wherein the fill structure laterally occupies more than 25% of the dicing line, wherein the periodic structure comprises a first periodicity with a first periodic pitch in the lateral direction and a second periodicity with a second periodic pitch in the perpendicular direction, wherein the first periodic pitch is a different pitch from the second periodic pitch. ### Claim 21 (depends on 20) The method for manufacturing according to claim 20, wherein the dicing line having a width smaller than 25 μm. ### Claim 22 (depends on 20) The method for manufacturing according to claim 20, wherein the periodic structure has a periodic pitch smaller than 5 μm. ### Claim 23 (depends on 20) The method for manufacturing according to claim 20, wherein the periodic structure is formed by a grid of metal vias or metal conductor line fragments. ### Claim 24 (depends on 20) The method for manufacturing according to claim 20, wherein the periodic structure is formed by a plurality of metal, oxide and/or polysilicon layers. ### Claim 25 (depends on 20) The method for manufacturing according to claim 20, wherein the fill structure comprises a density of metal of at least 10%. ### Claim 26 (depends on 20) The method for manufacturing according to claim 20, wherein the fill structure comprises a density of metal of at least 50%. ### Claim 27 (depends on 20) The method for manufacturing according to claim 20, wherein the chip areas are smaller than 3 mm2. ### Claim 28 (depends on 20) The method for manufacturing according to claim 20, wherein a width of each of the dicing lines is less than 100 μm.