# US 9,040,351 B2 · Stack packages having fastening element and halogen-free inter-package connector

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- Number: US 9,040,351 B2
- Document ID: US9040351B2
- Status: Granted
- Kind: B2
- Application number: 14/339,563
- Filed: 2014-07-24
- Published: 2014-11-13
- Granted: 2015-05-26
- Earliest claimed: 2011-05-02
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd
- Inventors: Heung-Kyu Kwon; Jae-Wook Yoo; Hyon-Chol Kim; Su-Chang Lee; Min-Ok Na
- Web page: https://patentgrep.com/patent/US9040351B2

## CPC

- H10W 90/00: Package configurations
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10W 40/251: {Organics}
- H10W 74/016: {using moulds}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 72/073: {of die-attach connectors}
- H10W 72/07341: {Controlling the bonding environment, e.g. atmosphere composition or temperature}
- H10W 72/552: {comprising metals or metalloids, e.g. silver}
- H10W 72/877: {Bump connectors and die-attach connectors}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 74/10: characterised by their shape or disposition
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/20: Configurations of stacked chips
- H10W 90/24: at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape
- H10W 90/26: the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/721: {of bump connectors}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/752: {between stacked chips}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A stack package includes a lower package including a lower package substrate and a lower semiconductor chip disposed on the lower package substrate, an upper package including an upper package substrate and an upper semiconductor chip disposed on the upper package substrate, a fastening element formed between a top surface of the lower semiconductor chip and a bottom surface of the upper package substrate, and a halogen-free inter-package connector connecting the lower package substrate to the upper package substrate.

## Claims

### Claim 1

A method of manufacturing a stack package, the method comprising:
forming a lower package comprising a lower package substrate, a first lower land disposed on a top surface of the lower package substrate, a lower inter-package connector disposed on the first lower land, and a lower semiconductor chip disposed on the top surface of the lower package substrate;
forming an upper package comprising an upper package substrate, a first upper land disposed on a bottom surface of the upper package substrate, an upper inter-package connector disposed on the first upper land, and an upper semiconductor chip disposed on a top surface of the upper package substrate;
providing an intermediate inter-package connector disposed on at least one of the lower inter-package connector and the upper inter-package connector;
providing a fastening element between the lower package and the upper package;
performing a first annealing to cure the fastening element; and
performing a second annealing to integrate the lower inter-package connector, the intermediate inter-package connector, and the upper inter-package connector,
wherein at least one of the first annealing and the second annealing removes at least one of an alcohol or a solvent from the intermediate inter-package connector to decrease a volume thereof.

### Claim 2 (depends on 1)

The method of claim 1, wherein the second annealing is performed at a higher temperature than the first annealing.

### Claim 3 (depends on 1)

The method of claim 1, wherein the lower inter-package connector and the upper inter-package connector each comprise tin, silver, and copper, and are substantially free of halogen-group elements.

### Claim 4 (depends on 1)

The method of claim 1, wherein the intermediate inter-package connector comprises an amount of halogen group elements no more than 1500 ppm.

### Claim 5 (depends on 4)

The method of claim 4, wherein the intermediate inter-package connector comprises no more than 900 ppm of bromine and chlorine.

### Claim 6 (depends on 1)

The method of claim 1, wherein the second annealing is performed at a temperature range of 230° C. to 250° C.

### Claim 7 (depends on 1)

The method of claim 1, wherein the second annealing is performed under a hydrogen and/or formic acid atmosphere.

### Claim 8 (depends on 1)

The method of claim 1, wherein the first annealing is performed at a temperature range of 125° C. to 175° C.

### Claim 9

A method of manufacturing a stack package, the method comprising:
preparing an upper package in which an upper semiconductor chip and an upper inter-package connector are disposed on opposite surfaces of an upper package substrate;
preparing a lower package in which a lower semiconductor chip and a lower inter-package connector are disposed on a same surface of a lower package substrate and a molding material contacts side surfaces of the lower semiconductor chip and contacts side surfaces of the lower inter-package connector, the molding material including an opening to expose a top surface of the lower inter-package connector;
providing a fastening element between a top surface of the lower semiconductor chip and a bottom surface of the upper package substrate; and
performing a first annealing to cure the fastening element and remove flux having a halogen element from the upper inter-package connector and the lower inter-package connector; and
performing a second annealing to integrate the upper inter-package connector and the lower inter-package connector,
wherein the first annealing is performed in a gas atmosphere containing hydrogen.

### Claim 10 (depends on 9)

The method of claim 9, wherein the second annealing heats the upper inter-package connector and the lower inter-package connector in a gas atmosphere containing hydrogen.

### Claim 11 (depends on 10)

The method of claim 10, wherein the gas containing hydrogen comprises hydrogen gas and/or formic acid gas.

### Claim 12 (depends on 10)

The method of claim 10, wherein the second annealing is performed at a temperature of 230 to 245° C.

### Claim 13 (depends on 9)

The method of claim 9, further comprising:
inserting the upper inter-package connector into the opening to connect the upper and lower inter-package connectors.

### Claim 14

A method of manufacturing a stack package, the method comprising:
preparing an upper package comprising:
an upper package substrate,
a first upper land and a upper semiconductor chip disposed on a top surface of the upper package substrate,
a second upper land disposed on a bottom surface of the upper package substrate, and
an upper inter-package connector disposed on the second upper land;
preparing a lower package comprising:
a lower package substrate,
a first lower land and a lower semiconductor chip disposed on a top surface of the lower package substrate,
a second lower land disposed on a bottom surface of the lower package substrate,
a lower inter-package connector disposed on the first lower land, and
a lower molding material surrounding side surfaces of the lower semiconductor chip, the lower molding material having an opening to expose a top surface of the lower inter-package connector;
providing a fastening element on a top surface of the lower semiconductor chip;
stacking the upper package on the lower package;
performing a first annealing process to cure the fastening element and remove flux having a halogen element from the upper inter-package connector and the lower inter-package connector;
performing a second annealing process to integrate and connect the upper inter-package connector and the lower inter-package connector.

### Claim 15 (depends on 14)

The method of claim 14, wherein the second annealing process is performed in a gas atmosphere containing hydrogen and not containing oxygen and nitrogen.

### Claim 16 (depends on 14)

The method of claim 14, further comprising:
placing the lower package on a low stack boat, the lower package having the fastening element on the lower semiconductor chip; and
pressing the upper package to the lower package using an upper stack boat during stacking the upper package on the lower package.

### Claim 17 (depends on 14)

The method of claim 14, wherein the lower package further comprises a solder on the second lower land.

### Claim 18 (depends on 14)

The method of claim 14, wherein the lower package further comprises an intermediate inter-package connector on the lower inter-package connector in the opening of the lower molding material.

### Claim 19 (depends on 18)

The method of claim 18, wherein the upper inter-package connector, the intermediate inter-package connector, and the lower inter-package connector are integrated during performing the second annealing process.

### Claim 20 (depends on 14)

The method of claim 14, wherein:
the lower molding material does not cover the top surface of the lower semiconductor chip, and
the fastening element is directly disposed on the top surface of the lower semiconductor chip.