# US 9,040,349 B2 · Method and system for a semiconductor device package with a die to interposer wafer first bond

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- Number: US 9,040,349 B2
- Document ID: US9040349B2
- Status: Granted
- Kind: B2
- Application number: 13/678,046
- Filed: 2012-11-15
- Published: 2014-05-15
- Granted: 2015-05-26
- Earliest claimed: 2012-11-15
- Assignees: Amkor Technology, Inc.
- Applicants: Michael G. Kelly; Ronald Patrick Huemoeller; Won Chul Do; David Jon Hiner
- Inventors: Michael G. Kelly; Ronald Patrick Huemoeller; Won Chul Do; David Jon Hiner
- Web page: https://patentgrep.com/patent/US9040349B2

## CPC

- H10W 70/635: {Through-vias}
- H10B 12/00: Dynamic random access memory [DRAM] devices
- H10P 54/00: Cutting or separating of wafers, substrates or parts of devices
- H10P 72/7402: {Wafer tapes, e.g. grinding or dicing support tapes}
- H10W 40/22: characterised by their shape, e.g. having conical or cylindrical projections
- H10W 70/095: {of vias therein}
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/657: {on sidewalls or bottom surfaces of the package substrates, interposers or redistribution layers}
- H10W 70/698: Semiconductor materials that are electrically insulating, e.g. undoped silicon
- H10W 74/014: {using batch processing}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 74/121: {by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation}
- H10W 90/00: Package configurations
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 95/00: Packaging processes not covered by the other groups of this subclass
- H10P 72/744: {Details of chemical or physical process used for separating the auxiliary support from a device or a wafer}
- H10W 72/0198: {batch processes}
- H10W 72/0711: {Apparatus therefor}
- H10W 72/07178: {Means for aligning}
- H10W 72/072: {of bump connectors}
- H10W 72/07207: {Temporary substrates, e.g. removable substrates}
- H10W 72/07227: {involving guiding structures, e.g. spacers or supporting members}
- H10W 72/07232: {Compression bonding, e.g. thermocompression bonding}
- H10W 72/07236: {Soldering or alloying}
- H10W 72/073: {of die-attach connectors}
- H10W 72/07332: {Compression bonding, e.g. thermocompression bonding}
- H10W 72/07338: {hardening the adhesive by curing, e.g. thermosetting}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/331: {Shapes of die-attach connectors}
- H10W 72/877: {Bump connectors and die-attach connectors}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 99/00: Subject matter not provided for in other groups of this subclass
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Methods and systems for a semiconductor device package with a die to interposer wafer first bond are disclosed and may include bonding a plurality of semiconductor die comprising electronic devices to an interposer wafer, and applying an underfill material between the die and the interposer wafer. A mold material may be applied to encapsulate the die. The interposer wafer may be thinned to expose through-silicon-vias (TSVs) and metal contacts may be applied to the exposed TSVs. The interposer wafer may be singulated to generate assemblies comprising the semiconductor die and an interposer die. The die may be placed on the interposer wafer utilizing an adhesive film. The interposer wafer may be singulated utilizing one or more of: a laser cutting process, reactive ion etching, a sawing technique, and a plasma etching process. The die may be bonded to the interposer wafer utilizing a mass reflow or a thermal compression process.

## Claims

### Claim 1

A method for semiconductor packaging, the method comprising:
applying an underfill material on an interposer wafer;
forming wells in the underfill material on the interposer wafer;
positioning a plurality of semiconductor die in relation to the interposer wafer utilizing a temporary adhesive film that is bonded to a first surface of the plurality of semiconductor die opposite a second surface of the plurality of semiconductor die, said second surface comprising micro-bumps;
bonding the plurality of semiconductor die to the interposer wafer by, at least in part, aligning the micro-bumps with the wells;
applying a mold material to encapsulate said plurality of semiconductor die;
thinning said interposer wafer to expose through-silicon-vias (TSVs);
applying metal contacts to said exposed TSVs;
singulating said interposer wafer to generate a plurality of assemblies each comprising one or more of said plurality of semiconductor die and an interposer die; and
bonding one or more of said plurality of assemblies to one or more packaging substrates.

### Claim 2 (depends on 1)

The method according to claim 1, wherein the adhesive film comprises an adhesive tape or compliant layer.

### Claim 3 (depends on 1)

The method according to claim 1, wherein the micro-bumps comprise copper.

### Claim 4 (depends on 1)

The method according to claim 1, wherein said singulating said interposer wafer comprises singulating said interposer wafer utilizing one or more of: a laser cutting process, reactive ion etching, a sawing technique, and a plasma etching process.

### Claim 5 (depends on 1)

The method according to claim 1, wherein said thinning said interposer wafer comprises thinning said interposer wafer after said plurality of semiconductor die have been bonded to said interposer wafer.

### Claim 6 (depends on 1)

The method according to claim 1, comprising removing at least said interposer wafer from a support substrate, said removing comprising:
forming a protective layer over backside bumps on said interposer wafer;
attaching a first chuck to said protective layer;
attaching a second chuck to said support substrate; and
causing relative motion between said attached first chuck and said attached second chuck.

### Claim 7 (depends on 1)

The method according to claim 1, wherein said micro-bumps comprise copper pillars.

### Claim 8 (depends on 1)

The method according to claim 1, wherein said forming wells comprises forming the wells only partially through the underfill material on said interposer wafer.

### Claim 9 (depends on 8)

The method according to claim 8, wherein said forming comprises forming the wells in the underfill material on the interposer wafer using one or more of photolithography and/or laser ablation.

### Claim 10 (depends on 1)

The method according to claim 1, wherein said applying an underfill material comprises applying said underfill material as a film.

### Claim 11 (depends on 1)

The method according to claim 1, wherein said bonding the plurality of semiconductor die to the interposer wafer comprises bonding the plurality of semiconductor die to said interposer wafer utilizing a mass reflow process.

### Claim 12 (depends on 1)

The method according to claim 1, wherein said bonding the plurality of semiconductor die to the interposer wafer comprises comprising bonding the plurality of semiconductor die to the interposer wafer utilizing a thermal compression process.

### Claim 13 (depends on 1)

The method according to claim 1, comprising bonding one or more additional die to said plurality of semiconductor die utilizing a mass reflow process.

### Claim 14 (depends on 1)

The method according to claim 1, comprising bonding one or more additional die to said plurality of semiconductor die utilizing a thermal compression process.

### Claim 15 (depends on 1)

The method according to claim 1, wherein said mold material comprises a polymer.

### Claim 16

A method for semiconductor packaging, the method comprising:
applying an underfill material to a front side of an interposer;
forming wells in the underfill material on the interposer;
bonding a first semiconductor die to the front side of the interposer by, at least in part, aligning micro-bumps on the semiconductor die with the wells formed in the underfill material;
applying a mold material to encapsulate said first semiconductor die;
thinning said interposer to expose through-silicon-vias (TSVs); and
applying metal contacts to said exposed TSVs.

### Claim 17 (depends on 16)

The method according to claim 16, comprising
bonding a second semiconductor die to the front side of the interposer;
singulating said interposer to generate a plurality of assemblies, and
bonding one or more of said plurality of assemblies to one or more packaging substrates,
wherein said plurality of assemblies comprise:
a first assembly comprising the first semiconductor die and a first interposer die singulated from the interposer; and
a second assembly comprising the second semiconductor die and a second interposer die singulated from the interposer.

### Claim 18 (depends on 16)

The method according to claim 16, wherein said thinning said interposer comprises thinning said interposer after said first semiconductor die has been bonded to said interposer.

### Claim 19 (depends on 16)

The method according to claim 16, wherein said forming wells comprises forming the wells only partially through the underfill material on the interposer.

### Claim 20

A method for semiconductor packaging, the method comprising:
applying an underfill material on an interposer wafer;
forming wells only partially through the underfill material on the interposer wafer;
positioning a plurality of semiconductor die in relation to said interposer wafer utilizing a temporary adhesive film that is bonded to a first surface of the plurality of semiconductor die opposite a second surface of the plurality of semiconductor die, said second surface comprising micro-bumps;
bonding said plurality of semiconductor die comprising electronic devices to a front side of said interposer wafer by, at least in part, aligning the micro-bumps with the well;
applying a mold material to encapsulate said plurality of semiconductor die;
applying metal contacts to through silicon vias (TSVs) exposed in said interposer wafer;
singulating said interposer wafer to generate a plurality of assemblies each comprising one or more of said plurality of semiconductor die and an interposer die; and
bonding one or more of said plurality of assemblies to one or more packaging substrates.