# US 9,040,348 B2 · Electronic assembly apparatus and associated methods

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- Number: US 9,040,348 B2
- Document ID: US9040348B2
- Status: Granted
- Kind: B2
- Application number: 13/607,481
- Filed: 2012-09-07
- Published: 2013-03-21
- Granted: 2015-05-26
- Earliest claimed: 2011-09-16
- Assignees: Altera Corporation
- Applicants: Nagesh Vodrahalli; Jon M. Long
- Inventors: Nagesh Vodrahalli; Jon M. Long
- Web page: https://patentgrep.com/patent/US9040348B2

## CPC

- H10W 90/00: Package configurations
- H10W 72/012: {of bump connectors, dummy bumps or thermal bumps}
- H10W 72/01235: {by plating, e.g. electroless plating or electroplating}
- H10W 72/01251: {Changing the shapes of bumps}
- H10W 72/01255: {by using masks}
- H10W 72/072: {of bump connectors}
- H10W 72/07232: {Compression bonding, e.g. thermocompression bonding}
- H10W 72/07252: {changes in structures or sizes}
- H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core}
- H10W 72/227: {Multiple bumps having different sizes}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/351: {Materials of die-attach connectors}
- H10W 72/877: {Bump connectors and die-attach connectors}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method of fabricating an electronic assembly includes fabricating first and second interconnects. The first interconnect is adapted to interconnect a first die to a substrate. The second interconnect is adapted to interconnect the first die to a second die. The method further includes assembling the first die, the second die, and the substrate together such that the first die is disposed above the substrate, and the second die is disposed below the first die.

## Claims

### Claim 1

A method of fabricating an electronic assembly, the method comprising:
fabricating, using a photolithography process, a first interconnect comprising a first set of copper pillars, the first interconnect to interconnect a first die to a semiconductor substrate;
fabricating, using the photolithography process, a second interconnect comprising a second set of copper pillars, the second interconnect to interconnect the first die to a second die; and
assembling the first die, the second die, and the semiconductor substrate together such that the first die is disposed above the semiconductor substrate, and the second die is disposed below the first die.

### Claim 2 (depends on 1)

The method according to claim 1, wherein fabricating the first and second interconnects further comprises fabricating the first and second sets of copper pillars such that the first set of copper pillars are taller than the second set of copper pillars.

### Claim 3 (depends on 2)

The method according to claim 2, wherein fabricating the first interconnect further comprises fabricating the first set of copper pillars on the first die.

### Claim 4 (depends on 3)

The method according to claim 3, wherein fabricating the second interconnect further comprises fabricating the second set of copper pillars on the first die.

### Claim 5 (depends on 3)

The method according to claim 3, wherein fabricating the second interconnect further comprises fabricating the second set of copper pillars on the second die.

### Claim 6 (depends on 1)

The method according to claim 1, wherein fabricating the first interconnect further comprises fabricating the first set of copper pillars on the semiconductor substrate.

### Claim 7 (depends on 6)

The method according to claim 6, wherein fabricating the second interconnect further comprises fabricating the second set of copper pillars on the first die.

### Claim 8 (depends on 6)

The method according to claim 6, wherein fabricating the second interconnect further comprises fabricating the second set of copper pillars on the second die.

### Claim 9 (depends on 1)

The method according to claim 1, wherein fabricating the second interconnect further comprises coupling analog circuitry fabricated in one of the first and second die to digital circuitry fabricated in the other of the first and second die.

### Claim 10 (depends on 1)

The method according to claim 1, wherein fabricating the second interconnect further comprises coupling analog or mixed-signal circuitry fabricated in one of the first and second die to digital circuitry fabricated in the other of the first and second die.

### Claim 11 (depends on 1)

The method according to claim 1, wherein fabricating the second interconnect further comprises coupling field programmable gate array (FPGA) circuitry fabricated in one of the first and second die to circuitry fabricated in the other of the first and second die.

### Claim 12

A method of fabricating an electronic assembly, the method comprising:
fabricating a first interconnect, the first interconnect to interconnect a first die to a substrate;
fabricating a second interconnect, the second interconnect to interconnect the first die to a second die;
fabricating a third interconnect, the third interconnect to interconnect the first die to a third die; and
assembling the first die, the second die, the third die, and the substrate together such that the first die is disposed above the substrate, the second die is disposed below the first die, and the third die is disposed below the first die,
wherein assembling the first die, the second die, the third die, and the substrate together further comprises disposing the second die between the first die and the third die.

### Claim 13 (depends on 11)

The method according to claim 11, wherein fabricating the first interconnect further comprises fabricating a first set of copper pillars, wherein fabricating the second interconnect further comprises fabricating a second set of copper pillars, and wherein fabricating the third interconnect further comprises fabricating a third set of copper pillars.

### Claim 14 (depends on 13)

The method according to claim 13, wherein the first set of copper pillars are taller than the second set of copper pillars.

### Claim 15 (depends on 14)

The method according to claim 14, wherein the second set of copper pillars are taller than the third set of copper pillars.

### Claim 16

A method of fabricating an electronic assembly, the method comprising:
fabricating, using a photolithography process, a first interconnect on a first die, the first interconnect comprising a first set of copper pillars;
fabricating, using a photolithography process, a second interconnect on the first die, the second interconnect comprising a second set of copper pillars;
interconnecting a second die to the first die using the second interconnect; and
interconnecting the first die to a semiconductor substrate using the first interconnect such that the first die and the second die are disposed above the substrate.

### Claim 17 (depends on 16)

The method according to claim 16, wherein interconnecting a second die to the first die using the second interconnect further comprises disposing the second die above the first die.

### Claim 18 (depends on 17)

The method according to claim 17, wherein interconnecting the first die to a substrate using the first interconnect such that the first die and the second die are disposed above the substrate further comprises using a flip chip technique.

### Claim 19 (depends on 16)

The method according to claim 16, wherein fabricating the first and second interconnects on the first die further comprises:
fabricating a first photoresist layer;
etching selectively the first photoresist layer to fabricate first and second sets of openings; and
depositing copper in the first and second sets of openings.

### Claim 20 (depends on 19)

The method according to claim 19, wherein fabricating the first and second interconnects on the first die further comprises performing a first planarization step.

### Claim 21 (depends on 19)

The method according to claim 19, wherein fabricating the first and second interconnects on the first die further comprises:
fabricating a second photoresist layer;
etching selectively the second photoresist layer to fabricate a third set of openings; and
depositing copper in the third set of openings.

### Claim 22 (depends on 21)

The method according to claim 21, wherein fabricating the first and second interconnects on the first die further comprises performing a second planarization step.

### Claim 23 (depends on 21)

The method according to claim 21, wherein fabricating the first and second interconnects on the first die further comprises etching the first and second photoresist layers.