# US 9,040,346 B2 · Semiconductor package and methods of formation thereof

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- Number: US 9,040,346 B2
- Document ID: US9040346B2
- Status: Granted
- Kind: B2
- Application number: 13/463,636
- Filed: 2012-05-03
- Published: 2013-11-07
- Granted: 2015-05-26
- Earliest claimed: 2012-05-03
- Assignees: Infineon Technologies AG
- Applicants: Ivan Nikitin; Edward Fuergut
- Inventors: Ivan Nikitin; Edward Fuergut
- Web page: https://patentgrep.com/patent/US9040346B2

## CPC

- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10P 52/00: Grinding, lapping or polishing of wafers, substrates or parts of devices
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W 40/00: Arrangements for thermal protection or thermal control (integrated devices comprising arrangements for thermal protection H10D89/60)
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 72/00: Interconnections or connectors in packages
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 90/00: Package configurations
- H10D 84/837: {comprising vertical IGFETs}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 72/01904: {using temporary auxiliary members, e.g. using sacrificial coatings or handle substrates}
- H10W 72/01935: {by plating, e.g. electroless plating or electroplating}
- H10W 72/0198: {batch processes}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/248: {Top-view layouts, e.g. mirror arrays}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/351: {Materials of die-attach connectors}
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/874: {On different surfaces}
- H10W 72/877: {Bump connectors and die-attach connectors}
- H10W 72/922: {Bond pads being integral with underlying chip-level interconnections}
- H10W 72/926: {Multiple bond pads having different sizes}
- H10W 72/9413: {on encapsulations}
- H10W 72/944: {Dispositions of multiple bond pads}
- H10W 72/9445: {Top-view layouts, e.g. mirror arrays}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/014: {using batch processing}
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 74/473: {containing a filler}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

In one embodiment, a semiconductor package includes a semiconductor chip having a first contact region on a first major surface and a second contact region on an opposite second major surface. The semiconductor chip is configured to regulate flow of a current from the first contact region to the second contact region. An encapsulant is disposed at the semiconductor chip. A first contact plug is disposed within the encapsulant and coupled to the first contact region. A second side conductive layer is disposed under the second major surface and coupled to the second contact region. A through via is disposed within the encapsulant and coupled to the second side conductive layer. The first contact plug and the through via form terminals above the first major surface for contacting the semiconductor package.

## Claims

### Claim 1

A method of forming a semiconductor package, the method comprising:
placing a plurality of semiconductor chips over a carrier, each of the plurality of semiconductor chips having a first side contact region on a first side and an opposite second side, each of the plurality of semiconductor chips having an active region adjacent the first side, wherein the second side faces the carrier;
forming a reconstituted wafer by applying an encapsulant at the plurality of semiconductor chips and the carrier;
forming a through opening and a first contact opening in the encapsulant using a common process step;
from the first side, forming a first contact via and a second contact via by filling the through opening and the first contact opening with a conductive fill material, wherein upper portions of the first contact via and the second contact via form contact pads for connecting each of the plurality of semiconductor chips to external nodes;
separating the reconstituted wafer from the carrier;
thinning the first contact via and the reconstituted wafer so as to thin the plurality of semiconductor chips from the second side; and
after the thinning, forming a second side conductive plate under a second side contact region from the second side, wherein the second side contact region is coupled to the first contact via through the second side conductive plate; and
forming individual packages by singulating the reconstituted wafer, wherein the plurality of semiconductor chips comprise chips configured to regulate current flow in a direction from the first side towards the second side.

### Claim 2 (depends on 1)

The method of claim 1, wherein placing a plurality of semiconductor chips over a carrier comprises placing a plurality of power chips and a plurality of devices, wherein each of the individual packages comprises a power chip of the plurality of power chips and a device of the plurality of devices.

### Claim 3 (depends on 2)

The method of claim 2, wherein the plurality of devices comprises a horizontal semiconductor device configured to regulate current flow laterally in a plane along the first side.

### Claim 4 (depends on 1)

The method of claim 1, wherein forming the through opening comprises using a laser drilling process.

### Claim 5 (depends on 1)

The method of claim 1, wherein forming the first contact via and the second contact via comprises using an electrochemical deposition process.

### Claim 6 (depends on 1)

The method of claim 1, wherein each of the plurality of semiconductor chips is configured to regulate current flow from the first side contact region to the second side contact region.

### Claim 7 (depends on 1)

The method of claim 1, wherein each of the plurality of semiconductor chips comprises a power field effect transistor, and wherein the first side contact region is a source region of the power field effect transistor and the second side contact region is a drain region of the power field effect transistor.

### Claim 8 (depends on 7)

The method of claim 7, further comprising:
forming a second contact opening in the encapsulant; and
forming a third contact via for a gate region of the power field effect transistor by filling the second contact opening with the conductive fill material.

### Claim 9 (depends on 1)

The method of claim 1, wherein forming the second side conductive plate comprises depositing a structured second side conductive plate using an electrochemical deposition process.

### Claim 10 (depends on 1)

The method of claim 1, wherein forming the second side conductive plate comprises depositing an unstructured second side conductive plate and structuring the unstructured second side conductive plate.

### Claim 11 (depends on 1)

The method of claim 1, wherein thinning the plurality of semiconductor chips comprises thinning a workpiece comprising a heteroepitaxial layer over a silicon substrate, and wherein the thinning removes the silicon substrate.

### Claim 12 (depends on 1)

The method of claim 1, wherein each of the plurality of semiconductor chips comprises an n-channel metal insulation semiconductor field effect transistor or a p-channel metal insulation semiconductor field effect transistor.

### Claim 13 (depends on 1)

The method of claim 1, wherein the semiconductor package has less than ten terminals.

### Claim 14

A method of forming a semiconductor package, the method comprising:
placing a plurality of power semiconductor chips over a carrier, each of the plurality of power semiconductor chips having a source contact region and a gate contact region on a first side and an opposite second side, each of the plurality of power semiconductor chips having an active region adjacent the first side, wherein the plurality of power semiconductor chips comprise chips configured to regulate vertical current flow in a direction from the first side towards the second side;
forming a reconstituted wafer by applying an encapsulant over the plurality of power semiconductor chips and the carrier;
forming a through opening in the encapsulant;
forming a first contact opening in the encapsulant over the source contact region and a second contact opening in the encapsulant over the gate contact region;
forming a first contact via by filling the through opening with a conductive fill material from the first side, wherein an upper portion of the first contact via forms a contact pad;
forming a second contact via and a third contact via by filling the first and the second contact openings with the conductive fill material;
thinning the first contact via and the plurality of power semiconductor chips by grinding the reconstituted wafer; and
after the thinning, forming a second side conductive plate under a drain contact region from the second side, wherein the drain contact region is coupled to the first contact via through the second side conductive plate wherein the second side conductive plate is formed from the second side opposite to the first side used to fill the through opening with the conductive fill material.

### Claim 15 (depends on 14)

The method of claim 14, further comprising forming individual packages by singulating the reconstituted wafer.

### Claim 16 (depends on 14)

The method of claim 14, wherein forming the through opening comprises using a laser drilling process.

### Claim 17 (depends on 14)

The method of claim 14, wherein the through opening and the first contact opening are formed using a common process.

### Claim 18 (depends on 14)

The method of claim 14, further comprising after forming the first, second, and the third contact vias, separating the reconstituted wafer from the carrier.

### Claim 19 (depends on 14)

The method of claim 14, wherein forming the second side conductive plate comprises depositing a structured second side conductive plate using an electrochemical deposition process.

### Claim 20 (depends on 14)

The method of claim 14, wherein forming the second side conductive plate comprises depositing an unstructured second side conductive plate and structuring the unstructured second side conductive plate.