# US 9,040,331 B2 · Diode-based devices and methods for making the same

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- Number: US 9,040,331 B2
- Document ID: US9040331B2
- Status: Granted
- Kind: B2
- Application number: 13/554,516
- Filed: 2012-07-20
- Published: 2012-11-08
- Granted: 2015-05-26
- Earliest claimed: 2009-01-09
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Anthony J. Lochtefeld
- Inventors: Anthony J. Lochtefeld
- Web page: https://patentgrep.com/patent/US9040331B2

## CPC

- H10D 8/01: Manufacture or treatment
- H10D 62/405: {Orientations of crystalline planes}
- H10F 71/121: {The active layers comprising only Group IV materials}
- H10F 71/1215: {comprising at least two Group IV elements, e.g. SiGe}
- H10F 71/1257: {comprising growth substrates not made of Group II-VI materials}
- H10F 71/133: {Providing edge isolation}
- H10F 77/14: Shape of semiconductor bodies; Shapes, relative sizes or dispositions of semiconductor regions within semiconductor bodies
- H10F 77/143: {comprising quantum structures}
- H10F 77/146: {Superlattices; Multiple quantum well structures}
- H10F 77/16: Material structures, e.g. crystalline structures, film structures or crystal plane orientations
- H10H 20/01: Manufacture or treatment
- H10H 20/014: {having light-emitting regions comprising only Group IV materials}
- H10H 20/812: within the light-emitting regions, e.g. having quantum confinement structures
- H10H 20/813: having a plurality of light-emitting regions, e.g. multi-junction LEDs or light-emitting devices having photoluminescent regions within the bodies
- H10H 20/818: within the light-emitting regions
- H10H 20/821: of the light-emitting regions, e.g. non-planar junctions
- H10P 14/24: using chemical vapour deposition [CVD]
- H10P 14/27: {using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials}
- H10P 14/271: {characterised by the preparation of substrate for selective deposition}
- H10P 14/2905: {Silicon, silicon germanium or germanium}
- H10P 14/3416: {Nitrides}
- H10P 14/3421: {Arsenides}
- H10D 8/755: {Resonant tunneling diodes [RTD]}
- H10D 62/40: Crystalline structures
- H10P 14/276: {Lateral overgrowth}
- H10P 14/3402: {characterised by the chemical composition}
- Y02E 10/541: CuInSe2 material PV cells
- Y02E 10/543: Solar cells from Group II-VI materials
- Y02E 10/544: Solar cells from Group III-V materials
- Y02E 10/547: Monocrystalline silicon PV cells
- Y02E 10/548: Amorphous silicon PV cells
- Y02P 70/50: Manufacturing or production processes characterised by the final manufactured product
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10H: INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- Y02E: REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02P: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS

## Abstract

In accordance with an embodiment, a diode comprises a substrate, a dielectric material including an opening that exposes a portion of the substrate, the opening having an aspect ratio of at least 1, a bottom diode material including a lower region disposed at least partly in the opening and an upper region extending above the opening, the bottom diode material comprising a semiconductor material that is lattice mismatched to the substrate, a top diode material proximate the upper region of the bottom diode material, and an active diode region between the top and bottom diode materials, the active diode region including a surface extending away from the top surface of the substrate.

## Claims

### Claim 1

A method of forming a diode, the method comprising:
depositing a layer of a dielectric material over a substrate, the dielectric material having a dielectric surface distal from the substrate;
patterning a first opening in the dielectric material to expose a first portion of the substrate, the first opening being through the dielectric surface of the dielectric material, the first opening having an aspect ratio of at least 1;
forming a first bottom diode region by growing a compound semiconductor material that is lattice mismatched to the substrate in and above the first opening, the first bottom diode region having a first sidewall surface extending above and away from the dielectric surface of the dielectric material;
forming a first active diode region directly adjacent the first sidewall surface of the first bottom diode region, the first active diode region having a second sidewall surface extending above and away from the dielectric surface of the dielectric material; and
forming a top diode region directly adjacent the second sidewall surface of the first active diode region in a plane parallel to the dielectric surface of the dielectric material intersecting the first bottom diode region, the first active diode region, and the top diode region.

### Claim 2 (depends on 1)

The method of claim 1 wherein the active diode region contains multiple quantum wells.

### Claim 3 (depends on 1)

The method of claim 1 wherein the substrate is selected from the group consisting of silicon, sapphire, and silicon carbide.

### Claim 4 (depends on 1)

The method of claim 1 wherein the opening is a trench and/or a hole.

### Claim 5 (depends on 1)

The method of claim 1 wherein the compound semiconductor material comprises a material selected from the group consisting essentially of a Group III-V compound, a Group II-VI compound, and a Group IV alloy.

### Claim 6 (depends on 1)

The method of claim 1 wherein the opening is a trench.

### Claim 7 (depends on 1)

The method of claim 1 further comprising:
patterning a second opening in the dielectric material to expose a second portion of the substrate, the second opening having an aspect ratio of at least 1;
forming a second bottom diode region by growing a compound semiconductor material that is lattice mismatched to the substrate in and above the second opening; and
forming a second active diode region adjacent the second bottom diode region, wherein the top diode region is formed laterally adjacent the second active diode region.

### Claim 8

A method of forming a diode, the method comprising:
depositing a layer of a dielectric material onto a substrate;
patterning first and second openings in the dielectric material to expose portions of the substrate, the first and second openings extending from an upper surface of the dielectric material to the substrate, each of the openings having an aspect ratio of at least 1;
forming a first bottom diode region by growing a compound semiconductor material that is lattice mismatched to the substrate in the first opening and above the upper surface of the dielectric material;
forming a second bottom diode region by growing a compound semiconductor material that is lattice mismatched to the substrate in the second opening and above the upper surface of the dielectric material;
forming a first active diode region adjacent the first bottom diode region;
forming a second active diode region adjacent the second bottom diode region; and
forming a single top diode region laterally adjacent the first active diode region and the second active diode region, the single top diode region directly adjoining the upper surface of the dielectric material between the first opening and the second opening.

### Claim 9 (depends on 8)

The method of claim 8 wherein the first and second active diode regions contain multiple quantum wells.

### Claim 10 (depends on 8)

The method of claim 8 wherein the substrate is selected from the group consisting of silicon, sapphire, and silicon carbide.

### Claim 11 (depends on 8)

The method of claim 8 wherein the substrate is a single crystal silicon wafer.

### Claim 12 (depends on 11)

The method of claim 11 wherein the substrate has a crystal orientation of (111) or (100).

### Claim 13 (depends on 8)

The method of claim 8 wherein the dielectric material comprises silicon dioxide or silicon nitride.

### Claim 14 (depends on 8)

The method of claim 8 wherein the first and second openings are trenches.

### Claim 15 (depends on 8)

The method of claim 8 wherein the first and second openings are holes.

### Claim 16 (depends on 8)

The method of claim 8 wherein the semiconductor material comprises a Group III-V compound.

### Claim 17 (depends on 8)

The method of claim 8 wherein the semiconductor material comprises a Group II-VI compound.

### Claim 18 (depends on 8)

The method of claim 8 wherein the semiconductor material comprises a Group IV alloy.

### Claim 19

A method comprising:
forming a dielectric layer over a substrate;
forming a first trench and a second trench in the dielectric layer to the substrate;
forming a first fin as a first bottom diode region, the first fin comprising a compound semiconductor material that is lattice mismatched to the substrate, the first fin being in the first trench and extending above the first trench, the first fin having a first sidewall extending away from the dielectric layer;
forming a second fin as a second bottom diode region, the second fin comprising a compound semiconductor material that is lattice mismatched to the substrate, the second fin being in the second trench and extending above the second trench, the second fin having a second sidewall extending away from the dielectric layer, a plane intersecting the first sidewall of the first fin and the second sidewall of the second fin;
forming a first active diode region adjacent the first sidewall of the first fin, the first active diode region having a third sidewall extending away from the dielectric layer;
forming a second active diode region adjacent the second sidewall of the second fin, the second active diode region having a fourth sidewall extending away from the dielectric layer; and
forming a top diode region disposed at least in part between the third sidewall of the first active diode region and the fourth sidewall of the second active diode region, the plane further intersecting the third sidewall of the first active diode region, the fourth sidewall of the second active diode region, and the top diode region disposed at least in part between the third sidewall and the fourth sidewall.

### Claim 20 (depends on 19)

The method of claim 19, wherein an aspect ratio of each of the first trench and the second trench is at least 1.