# US 9,040,315 B2 · Method for planarizing semiconductor devices

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- Number: US 9,040,315 B2
- Document ID: US9040315B2
- Status: Granted
- Kind: B2
- Application number: 13/921,220
- Filed: 2013-06-19
- Published: 2014-12-25
- Granted: 2015-05-26
- Earliest claimed: 2013-06-19
- Assignees: United Microelectronics Corp.
- Applicants: United Microelectronics Corporation
- Inventors: Yi-Ching Wu; Tzu-Hung Yang; Chih-Chung Wu
- Web page: https://patentgrep.com/patent/US9040315B2

## CPC

- H10P 52/402: {of semiconductor materials}
- B24B 37/042: {operating processes therefor}
- B24B 49/006: {taking regard of the speed}
- H10P 95/062: {involving a dielectric removal step}
- H10P 74/203: {Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects}
- H10P 74/238: {comprising acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection or in-situ thickness measurement}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- B24B: MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING (grinding of gear teeth B23F, of screw-threads B23G1/36; by electro-erosion B23H; abrasive or related blasting B24C; tools for grinding, buffing or sharpening B24D; polishing compositions C09G1/00; abrasives C09K3/14; electrolytic etching or polishing C25F3/00; grinding arrangements for use on assembled railway tracks E01B31/17); DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS

## Abstract

A method for planarizing semiconductor devices, wherein the method comprises steps as follows: At least one patterned metal layer is formed on a substrate. A material layer having a first area and a second area is provided on the patterned metal layer and the substrate, in which there is a step height existing between the first area and the second area. A first polishing process having a first selection ratio of relative speeds for removing the material layer at the first area to that at the second area is then performed on the material layer. Subsequently, a second polishing process having a second selection ratio of relative speeds for removing the material layer at the first area to that at the second area is performed on the material layer, and the second selection ratio is greater than the first selection ratio.

## Claims

### Claim 1

A method for planarizing semiconductor devices comprising:
forming at least one patterned metal layer on a substrate;
providing a material layer having a first area and a second area on the at least one patterned metal layer and the substrate, wherein there is a step height existing between the first area and the second area;
performing a first polishing process on the material layer, wherein the first polishing process has a first selection ratio of relative speeds for removing the material layer at the first area to that at the second area; and
performing a second polishing process on the material layer, wherein the second polishing process has a second selection ratio of relative speeds for removing the material layer at the first area to that at the second area, and the second selection ratio is greater than the first selection ratio;
wherein the second polishing process comprises a second slurry comprising a buffer reagent comprising a re-dispersible polymer.

### Claim 2 (depends on 1)

The method for planarizing semiconductor devices according to claim 1, wherein the first polishing process comprises a first slurry having silicon dioxide (SiO2) ranging from 0.95% to 1.05% by weight.

### Claim 3 (depends on 2)

The method for planarizing semiconductor devices according to claim 2, wherein the first selection ratio is about 1:7.

### Claim 4 (depends on 1)

The method for planarizing semiconductor devices according to claim 1, wherein the second selection ratio is about 1:30.

### Claim 5 (depends on 1)

The method for planarizing semiconductor devices according to claim 1, each of the first polishing process and the second polishing process comprises utilizing an optical monitoring system to determine an end-point of the first polishing process and the second polishing process, respectively.

### Claim 6 (depends on 5)

The method for planarizing semiconductor devices according to claim 5, wherein the first polishing process is ended when the step height is reduced by half.

### Claim 7 (depends on 6)

The method for planarizing semiconductor devices according to claim 6, wherein the second polishing process is ended when the step height is equal to 0.

### Claim 8 (depends on 1)

The method for planarizing semiconductor devices according to claim 1, wherein the first polishing process is ended after performing first polishing process for a predetermined first polishing time.

### Claim 9 (depends on 8)

The method for planarizing semiconductor devices according to claim 8, wherein the second polishing process is ended after performing the second polishing process for a predetermined second polishing time.

### Claim 10 (depends on 1)

The method for planarizing semiconductor devices according to claim 1, wherein the material layer is a dielectric layer.