# US 9,039,427 B2 · Interdigitated chip capacitor assembly

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- Number: US 9,039,427 B2
- Document ID: US9039427B2
- Status: Granted
- Kind: B2
- Application number: 13/767,009
- Filed: 2013-02-14
- Published: 2014-08-14
- Granted: 2015-05-26
- Earliest claimed: 2013-02-14
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Allan Jerome Daen Rapales; Floro Lopez Camenforte, III; John Paul Quianzon Kwo
- Web page: https://patentgrep.com/patent/US9039427B2

## CPC

- H05K 3/3442: {having edge contacts, e.g. leadless chip capacitors, chip carriers}
- H01G 2/065: {for surface mounting, e.g. chip capacitors}
- H01G 4/232: electrically connecting two or more layers of a stacked or rolled capacitor
- H05K 1/18: structurally associated with non-printed electric components (H05K1/16 takes precedence)
- H05K 1/183: associated with components mounted in and supported by recessed areas of the PCBs
- H05K 3/0014: {Shaping of the substrate, e.g. by moulding}
- H05K 3/301: {by means of a mounting structure (H05K3/325 takes precedence)}
- H05K 3/3452: Solder masks
- H01G 4/30: Stacked capacitors (H01G4/33 takes precedence)
- H05K 2201/0162: Silicon containing polymer, e.g. silicone
- H05K 2201/09036: Recesses or grooves in insulating substrate
- H05K 2201/09172: Notches between edge pads
- H05K 2201/09909: Special local insulating pattern, e.g. as dam around component
- H05K 2203/0126: Dispenser, e.g. for solder paste, for supplying conductive paste for screen printing or for filling holes
- H05K 2203/046: Means for drawing solder, e.g. for removing excess solder from pads
- H05K 2203/167: Using mechanical means for positioning, alignment or registration, e.g. using rod-in-hole alignment
- H05K 2203/168: Wrong mounting prevention
- Y02P 70/50: Manufacturing or production processes characterised by the final manufactured product
- Y10T 29/43: Electric condenser making
- Y10T 29/49135: and shaping, e.g., cutting or bending, etc.
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H01G: CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE (selection of specified materials as dielectric H01B3/00; capacitors having potential barriers H10D1/62, H10K10/10)
- Y02P: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y10T: TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION

## Abstract

An interdigitated chip capacitor (“IDC”) assembly including an IDC having a semiconductor block with a top portion, a bottom portion opposite the top portion, a plurality of sidewall portions extending between the top and bottom portions, and a plurality of terminals located on the sidewall portions; and a substrate having a top portion with a plurality of generally flat, vertically extending, nonconductive abutment surfaces thereon, the sidewall portions of the IDC being abuttingly engaged with at least some of the plurality of abutment surfaces.

## Claims

### Claim 1

An interdigitated chip capacitor (“IDC”) assembly comprising:
an IDC comprising:
a semiconductor block with a top portion, a bottom portion opposite said top portion and a plurality of sidewall portions extending between said top and bottom portions; and
a plurality of terminals located on said sidewall portions; and
a substrate a top portion with a plurality of nonconductive vertically extending abutment surfaces thereon, further comprising a plurality of recess wall portions defining a central recess therein, wherein said substrate top portion comprises a plurality of grooves projecting outwardly from said central recess;
said sidewall portions of said IDC being abuttingly engaged with at least some of said plurality of abutment surfaces.

### Claim 2 (depends on 1)

The assembly of claim 1 wherein said substrate further comprises:
a plurality of contact pads arranged in a predetermined pattern corresponding to said plurality of terminals of said IDC; and
a plurality of solder beads bonded to said plurality of contact pads and said plurality of terminals.

### Claim 3 (depends on 1)

The assembly of claim 1 wherein said central recess has a footprint corresponding to said bottom portion of said semiconductor block.

### Claim 4 (depends on 1)

The assembly of claim 1 wherein said substrate comprises:
a plurality of contact pads arranged in a predetermined pattern corresponding to said plurality of terminals of said IDC; and
a plurality of solder beads bonded to said plurality of contact pads and said plurality of terminals;
wherein said plurality of contact pads are located in said plurality of grooves.

### Claim 5 (depends on 1)

The assembly of claim 1 wherein said substrate comprises:
a plurality of contact pads arranged in a predetermined pattern corresponding to said plurality of terminals of said IDC; and
a plurality of solder beads bonded to said plurality of contact pads and said plurality of terminals;
wherein said plurality of contact pads are each located adjacent to at least one of said plurality of grooves.

### Claim 6 (depends on 2)

The assembly of claim 2 wherein at least some of said abutment surfaces are positioned between adjacent ones of said plurality of solder beads.

### Claim 7 (depends on 5)

The assembly of claim 5, said plurality of nonconductive vertically extending abutment surfaces comprising surface portions of said solder beads.

### Claim 8 (depends on 5)

The assembly of claim 5 wherein said plurality of grooves each have a depth greater than the depth of said central recess.