# US 9,038,883 B2 · VCSEL packaging > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,038,883 B2 - Document ID: US9038883B2 - Status: Granted - Kind: B2 - Application number: 14/479,325 - Filed: 2014-09-07 - Published: 2015-03-12 - Granted: 2015-05-26 - Earliest claimed: 2013-09-11 - Assignees: Princeton Optronics, Inc. - Applicants: Princeton Optronics Inc. - Inventors: Qing Wang; Jean-Francois Seurin; Chuni Lal Ghosh; Laurence Watkins - Web page: https://patentgrep.com/patent/US9038883B2 ## CPC - H01S 5/0237: by soldering - B23K 1/0016: {Soldering of electronic components} - B23K 1/012: Soldering with the use of hot gas - H01S 5/423: {having a vertical cavity} - H05K 3/3436: {having an array of bottom contacts, e.g. pad grid array or ball grid array components} - H05K 3/3494: Heating processes for reflow soldering - B23K 2101/42: Printed circuits - H01S 5/0042: {On wafer testing, e.g. lasers are tested before separating wafer into chips} - H01S 5/02345: Wire-bonding - H05K 1/0206: {by printed thermal vias} - H05K 2201/10121: Optical component, e.g. opto-electronic component - H05K 2201/10727: Leadless chip carrier [LCC], e.g. chip-modules for cards - H05K 2203/085: Using vacuum or low pressure - H10W 72/5445: {being orthogonal to a side surface of the chip, e.g. parallel arrangements} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - Y02P 70/50: Manufacturing or production processes characterised by the final manufactured product - H01S: DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL - B23K: SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM - H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - Y02P: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS ## Abstract A process to bond VCSEL arrays to submounts and printed circuit boards is provided. The process is particularly suited to large area thin and ultra-thin VCSEL arrays susceptible to bending and warping. The process integrates a flatness measurement step and applying appropriate combination of pressure prior to bonding the VCSEL array to the submount or a printed circuit using a vacuum flux-less bonding process. The process is very promising in making very good quality bonding between the VCSEL array and a submount or a printed circuit board. The process is applied to construct optical modules with improved flatness that may be integrated with other electronic components in constructing optoelectronic systems. ## Claims ### Claim 1 A packaging process comprising the steps of: positioning and aligning a submount in a vacuum soldering apparatus, wherein said submount is a thermal submount, a printed circuit board or a combination thereof; aligning a VCSEL chip including a plurality of VCSELs, in a pre-determined reference with the submount such that a plurality of bonding pads on the submount align substantially with corresponding plurality of contact pads on the VCSEL chip; correcting for a curvature of the VCSEL chip surface by applying a pre-determined amount of pressure effected through a structured pad with raised regions to differentially apply controlled pressure on predetermined locations of the VCSEL chip surface to facilitate said step of correcting for the curvature; sealing the vacuum soldering apparatus for enclosing the submount and the VCSEL chip; creating an air free environment in the vacuum soldering apparatus; and heating the submount and the VCSEL chip in close contact thereby facilitating bonding, such that the VCSEL chip is bonded substantially flat on the submount. ### Claim 2 (depends on 1) The packaging process as in claim 1, wherein said steps of aligning is in reference with pre-determined alignment features with respect to an inner chamber of the vacuum soldering apparatus. ### Claim 3 A packaging process comprising the steps of: positioning and aligning a submount in a vacuum soldering apparatus; aligning a VCSEL chip including a plurality of VCSELs, in a pre-determined reference with the submount such that a plurality of bonding pads on the submount align substantially with corresponding plurality of contact pads on the VCSEL chip; measuring curvature of the VCSEL chip surface, wherein said step of measuring curvature of the VCSEL chip surface is effected through measuring an angle of reflection across the VCSEL chip surface in response to a radiation incident upon said VCSEL chip surface at a fix angle; correcting for the curvature of the VCSEL chip surface by applying pre-determined amount of pressure; sealing the vacuum soldering apparatus for enclosing the submount and the VCSEL chip; creating an air free environment in the vacuum soldering apparatus; and heating the submount and the VCSEL chip in close contact thereby facilitating bonding, such that the VCSEL chip is bonded substantially flat on the submount. ### Claim 4 (depends on 1) The packaging process as in claim 1, wherein the step of applying pressure using the structured pad on the VCSEL chip surface is facilitated by one or more spacer. ### Claim 5 (depends on 1) The packaging process as in claim 1, wherein the step of applying pressure using the structured pad on the VCSEL chip surface is facilitated by a spring. ### Claim 6 (depends on 1) The packaging process as in claim 1, wherein bonding is facilitated through providing solder between plurality of bonding pads on the submount and corresponding plurality of contact pads on the VCSEL chip. ### Claim 7 (depends on 1) The packaging process as in claim 1, wherein said step of heating is performed in one or more heating cycles to facilitate an iterative process of correcting for curvature and re-flow of solder between the plurality of bonding pads on the submount and corresponding plurality of contact pads on the VCSEL chip to attain a desired quality of flatness and bonding. ### Claim 8 (depends on 3) The packaging process as in claim 3, wherein said steps of measuring curvature and correcting for the curvature are performed iteratively in a test run loop to determine a set of pressure values suitable for the measured curvature of the VCSEL chip. ### Claim 9 (depends on 1) The packaging process as in claim 1, wherein air free environment is one selected from the group consisting of vacuum, inert gas and a gas providing a reducing environment. ### Claim 10 A packaging process comprising the steps of: positioning and aligning a printed circuit board in a vacuum soldering apparatus; aligning a VCSEL chip including a plurality of VCSELs, in a pre-determined reference with the printed circuit board such that a plurality of contact pads on the printed circuit board align substantially with corresponding plurality of contact pads on the VCSEL chip; measuring curvature of the surface of the VCSEL chip surface, wherein said step of measuring curvature of the VCSEL chip surface is effected through measuring an angle of reflection across the VCSEL chip surface in response to a radiation incident upon said VCSEL chip surface at a fix angle; correcting for the curvature of the VCSEL chip surface by applying pre-determined amount of pressure; sealing the vacuum soldering apparatus for enclosing the printed circuit board and the VCSEL chip; creating an air free environment in the vacuum soldering apparatus; and heating the printed circuit board and the VCSEL chip in close contact thereby facilitating bonding, such that the VCSEL chip is bonded substantially flat on the submount. ### Claim 11 (depends on 10) The packaging process as in claim 10, wherein said steps of aligning is in reference with pre-determined alignment features with respect to an inner chamber of the vacuum soldering apparatus. ### Claim 12 (depends on 10) The packaging process as in claim 10, wherein the step of applying pressure on the VCSEL chip surface is facilitated by one or more spacers in conjunction with a spring. ### Claim 13 (depends on 10) The packaging process as in claim 10, wherein said step of applying pressure is further effected through a structured pad designed to apply pressure differentially on pre-determined locations of the VCSEL chip surface to facilitate said step of correcting for the curvature. ### Claim 14 (depends on 10) The packaging process as in claim 10, wherein bonding is facilitated through providing solder between plurality of bonding pads on the printed circuit board and corresponding plurality of contact pads on the VCSEL chip. ### Claim 15 (depends on 10) The packaging process as in claim 10, wherein said step of heating is performed in one or more heating cycles to facilitate an iterative process of correcting for curvature and re-flow of solder between the plurality of bonding pads on the submount and corresponding plurality of contact pads on the VCSEL chip to attain a desired quality of flatness and bonding. ### Claim 16 A packaging process comprising the steps of: positioning and aligning a printed circuit board in a vacuum soldering apparatus; aligning a VCSEL chip including a plurality of VCSELs, in a pre-determined reference with the printed circuit board such that a plurality of contact pads on the printed circuit board align substantially with corresponding plurality of contact pads on the VCSEL chip; measuring curvature of the surface of the VCSEL chip surface, wherein said step of measuring curvature of the VCSEL chip surface is effected through measuring an angle of reflection across the VCSEL chip surface in response to a radiation incident upon said VCSEL chip surface at a fix angle; correcting for the curvature of the VCSEL chip surface by applying pre-determined amount of pressure, wherein said steps of measuring curvature and correcting of curvature are performed iteratively in a test run loop to determine a set of pressure values suitable for the measured curvature of the VCSEL chip surface; sealing the vacuum soldering apparatus for enclosing the printed circuit board and the VCSEL chip; creating an air free environment in the vacuum soldering apparatus; and heating the printed circuit board and the VCSEL chip in close contact thereby facilitating bonding, such that the VCSEL chip is bonded substantially flat on the submount. ### Claim 17 (depends on 10) The packaging process as in claim 10, wherein air free environment is one selected from the group consisting of vacuum, inert gas and a gas providing a reducing environment. ### Claim 18 (depends on 3) The packaging process as in claim 3, wherein said submount is one selected from the group consisting of a thermal submount, a printed circuit board or a combination thereof. ### Claim 19 (depends on 3) The packaging process as in claim 3, wherein said steps of aligning is in reference with pre-determined alignment features with respect to an inner chamber of the vacuum soldering apparatus. ### Claim 20 (depends on 3) The packaging process as in claim 3, wherein the step of applying pressure on the VCSEL chip surface is facilitated by one or more spacers in conjunction with a spring. ### Claim 21 (depends on 3) The packaging process as in claim 3, wherein said step of applying pressure is further effected through a structured pad designed to apply pressure differentially on pre-determined locations of the VCSEL chip surface to facilitate said step of correcting for the curvature. ### Claim 22 (depends on 3) The packaging process as in claim 3, wherein bonding is facilitated through providing solder between plurality of bonding pads on the submount and corresponding plurality of contact pads on the VCSEL chip. ### Claim 23 (depends on 3) The packaging process as in claim 3, wherein said step of heating is performed in one or more heating cycles to facilitate an iterative process of correcting for curvature and re-flow of solder between the plurality of bonding pads on the submount and corresponding plurality of contact pads on the VCSEL chip to attain a desired quality of flatness and bonding. ### Claim 24 (depends on 16) The packaging process as in claim 16, wherein said steps of aligning is in reference with pre-determined alignment features with respect to an inner chamber of the vacuum soldering apparatus. ### Claim 25 (depends on 16) The packaging process as in claim 16, wherein the step of applying pressure on the VCSEL chip surface is facilitated by one or more spacers in conjunction with a spring. ### Claim 26 (depends on 16) The packaging process as in claim 16, wherein said step of applying pressure is further effected through a structured pad designed to apply pressure differentially on pre-determined locations of the VCSEL chip surface to facilitate said step of correcting for the curvature. ### Claim 27 (depends on 16) The VCSEL packaging process as in claim 16, wherein bonding is facilitated through providing solder between plurality of bonding pads on the submount and corresponding plurality of contact pads on the VCSEL chip. ### Claim 28 (depends on 16) The VCSEL packaging process as in claim 16, wherein said step of heating is performed in one or more heating cycles to facilitate an iterative process of correcting for curvature and re-flow of solder between the plurality of bonding pads on the submount and corresponding plurality of contact pads on the VCSEL chip to attain a desired quality of flatness and bonding.