Bandgap reference circuit and regulator circuit with common amplifier

A bandgap voltage reference and voltage regulator system, comprising:

• a bandgap voltage reference circuit;
• a voltage regulator circuit having a driver stage;
• an operational amplifier having an inverted input and a non-inverted input, wherein the operation amplifier is connected between the bandgap voltage reference circuit and the voltage regulator circuit, wherein the operational amplifier is shared by the bandgap voltage reference circuit and the voltage regulator circuit, and wherein the operational amplifier operates as a gain stage for the bandgap voltage reference circuit, and as an error amplifier for the driver stage of the voltage regulator circuit;
• and
• a start-up circuit directly connected to the inverted and non-inverted inputs of the operational amplifier, and to the output of the operational amplifier for detecting a regulator output voltage level and bringing up the system to a predetermined operating point,
• wherein the operational amplifier comprises:
• a first stage including the inverted and non-inverted inputs of the operational amplifier;
• a second stage connected to the first stage, for providing a drive voltage (Vdriver) at the output of the operational amplifier;
• and
• a current reference stage connected to the second stage and comprising elements from the first stage of the operational amplifier,
• wherein the first stage of the operational amplifier comprises:
• an input differential section including first and second input differential section transistors;
• a load section including first and second load section transistors;
• and
• a tail current source section including a tail current source section transistor, wherein:
• the first input differential section transistor has a source connected to a source of the second input differential section transistor and to a drain of the tail current source section transistor, a gate connected to the inverted input of the operational amplifier, and a drain connected to a drain of the first load section transistor,
• the second input differential section transistor has a gate connected to the non-inverted input of the operational amplifier, and a drain connected to a drain of the second load section transistor,
• the first load section transistor has a gate connected to its drain and to a gate of the second load section transistor, and a source connected to a source of the second load section transistor and to a common ground (Vss),
• the tail current source section transistor has a gate connected to the second stage and a source connected to a supply voltage (Vdd), and
• wherein an output of the first stage is generated at a node between the drains of the second input differential section transistor and the second load section transistor.