Semiconductor-on-insulator with back side heat dissipation
AssigneeSilanna Semiconductor U.S.A., Inc.
InventorsPaul A. Nygaard, Stuart B. Molin, Michael A. Stuber
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Abstract
Embodiments of the present invention provide for the dissipation of heat from semiconductor-on-insulator (SOI) structures. In one embodiment, a method for fabricating an integrated circuit is disclosed. In a first step, active circuitry is formed in an active layer of a SOI wafer. In a second step, substrate material is removed from a substrate layer disposed on a back side of the SOI wafer. In a third step, insulator material is removed from the back side of the SOI wafer to form an excavated insulator region. In a fourth step, a thermal dissipation layer is deposited on said excavated insulator region. The thermal dissipation layer is thermally conductive and electrically insulating.
Claims22
A method of fabricating an integrated circuit, the method comprising:
- preparing a semiconductor-on-insulator wafer for processing, said semiconductor-on-insulator wafer having an active layer, an insulator layer, and a substrate;
- forming an active device in said active layer, said active device having a gate region, a source region, a drain region, and a channel region, said channel region being located below said gate region and between said source region and said drain region;
- bonding a handle wafer to a top side of said semiconductor-on-insulator wafer;
- after bonding said handle wafer to said semiconductor-on-insulator wafer, removing said substrate from a backside of said semiconductor-on-insulator wafer;
- forming an excavated insulator region in said insulator layer from a back side of said semiconductor-on-insulator layer, said excavated insulator region exposing a portion of said active device;
- and
- depositing an electrically insulating thermal dissipation layer on said excavated insulator region;
- wherein said excavated insulator region defines a remaining section of insulator material that is laterally coextensive with said channel region of said active device.
A method of fabricating an integrated circuit, the method comprising:
- providing a semiconductor-on-insulator wafer, said semiconductor-on-insulator wafer having an active layer, an insulator layer, and a substrate;
- forming an active device in said active layer, said active device having a gate region, a source region, a drain region, and a channel region, said channel region being located below said gate region and between said source region and said drain region;
- bonding a handle wafer to said semiconductor-on-insulator wafer;
- after bonding said handle wafer to said semiconductor-on-insulator wafer, removing a portion of said substrate from said semiconductor-on-insulator wafer using a chemical etch;
- after removing said substrate from said semiconductor-on-insulator wafer, removing a portion of said insulator layer from a back side of said semiconductor-on-insulator wafer to form an excavated insulator region and to leave an unexcavated insulator region;
- and
- depositing a thermal dissipation layer on said excavated insulator region;
- wherein said unexcavated insulator region is laterally coextensive with said channel region of said active device, and exposes a portion of said active device.
A method of fabricating an integrated circuit, the method comprising:
- providing a semiconductor-on-insulator wafer, said semiconductor-on-insulator wafer having an active layer, an insulator layer, and a substrate;
- forming an active device in said active layer, said active device having a gate region, a source region, a drain region, and a channel region, said channel region being located below said gate region and between said source region and said drain region;
- bonding a handle wafer to said semiconductor-on-insulator wafer;
- after bonding said handle wafer to said semiconductor-on-insulator wafer, removing said substrate from said semiconductor-on-insulator wafer;
- after removing said substrate from said semiconductor-on-insulator wafer, uniformly removing said insulator layer from a back side of said semiconductor-on-insulator wafer;
- passivating a group of interface states by using a low temperature thermal anneal, said group of interface states being located on said back side of said semiconductor-on-insulator wafer;
- and
- after removing said insulator layer from said back side of said semiconductor-on-insulator wafer, depositing a thermal dissipation layer on said back side of said semiconductor-on-insulator wafer;
- wherein said thermal dissipation layer comprises a same material as said insulator layer.
Dependencies are inferred from the claim text.