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US 9,023,712 B2Granted
Method for self-aligned removal of a high-K gate dielectric above an STI region
AssigneeAdvanced Micro Devices, Inc.
InventorsAndy Wei, Roman Boschke, Markus Forsberg
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Abstract
By forming a trench isolation structure after providing a high-k dielectric layer stack, direct contact of oxygen-containing insulating material of a top surface of the trench isolation structure with the high-k dielectric material in shared polylines may be avoided. This technique is self-aligned, thereby enabling further device scaling without requiring very tight lithography tolerances. After forming the trench isolation structure, the desired electrical connection across the trench isolation structure may be re-established by providing a further conductive material.
Claims20
A method, comprising:
- forming a gate layer stack above a semiconductor layer, said gate layer stack comprising a high-k dielectric layer and a metal-containing material formed on said high-k dielectric layer;
- forming a trench isolation structure in said gate layer stack, said trench isolation structure extending through said gate layer stack and into said semiconductor layer to isolate a first active region from a second active region;
- forming a first gate electrode of a first transistor above said first active region and a second gate electrode of a second transistor above said second active region;
- and
- forming a conductive material above said metal-containing material and directly overlying a top surface of said trench isolation structure, said conductive material forming an electrically conductive connection between said first gate electrode and said second gate electrode.
2 more elements
A method, comprising:
- forming a gate layer stack on a semiconductor layer, said gate layer stack comprising a high-k dielectric material and covering a first active region and a second active region;
- forming a trench isolation structure that extends through said gate layer stack and into said semiconductor layer so as to isolate said first and second active regions from each other and to provide a first portion of said gate layer stack and a second portion of said gate layer stack;
- forming a conductive connection between said first and second portions of said gate layer stack above said trench isolation structure, said conductive connection directly overlying a top surface of the trench isolation structure;
- and
- forming a first transistor in and above said first active region and a second transistor in and above said second active region.
2 more elements
A method, comprising:
- forming a gate layer stack above a semiconductor layer, wherein forming said gate layer stack comprises forming a high-k dielectric material layer above said semiconductor layer, forming a metal-containing material layer above said high-k dielectric material layer, and forming a first conductive material layer above said metal-containing material layer;
- forming a trench isolation structure through said gate layer stack to isolate a first active region from a second active region, wherein an upper end of said trench isolation structure extends at least partially into said first conductive material layer above said metal-containing material layer and a lower end of said trench isolation structure extends at least partially into said semiconductor layer below said high-k dielectric material layer;
- forming a first gate electrode of a second transistor above said second active region from said gate layer stack;
- forming a second gate electrode of a second transistor above said second active region from said gate layer stack;
- and
- forming a second conductive material layer above said first conductive material layer and directly overlying a top surface of said trench isolation structure, said second conductive material layer forming an electrically conductive connection between said first gate electrode and said second gate electrode.
3 more elements
Dependencies are inferred from the claim text.