Phase-to-amplitude converter for direct digital synthesizer (DDS) with reduced AND and reconstructed ADD logic arrays

A digital wave synthesizer comprising:

• a phase input;
• a quadrant folder and phase splitter, receiving the phase input, for outputting a Most-Significant-Bit (MSB), and for splitting the phase input into a lower phase having Least-Significant-Bits (LSBs), an upper phase having a higher significance than the lower phase, and a delta bit between the upper phase and the lower phase;
• a quadrant reflector for conditionally inverting the upper phase, the delta bit, and the lower phase in response to a penultimate MSB from the phase input;
• a coarse table for outputting a coarse value stored for a current value of the upper phase from the quadrant reflector;
• a slope table for outputting a slope value stored for the current value of the upper phase from the quadrant reflector;
• a lower inverter for inverting the lower phase when the delta bit is in a first state to generate a conditionally inverted lower phase;
• an upper inverter for inverting the coarse value when the delta bit is in the first state to generate a conditionally inverted coarse value;
• first logic for combining the slope value from the slope table with the conditionally inverted lower phase from the upper inverter to generate a slope-phase value;
• second logic for combining the conditionally inverted coarse value from the upper inverter with the slope-phase value from the first logic to generate a wave amplitude;
• and
• a sign inverter, receiving the MSB from the quadrant folder, for inverting the MSB to generate a sign bit when the delta bit is in the first state, wherein the sign bit indicates a polarity of the wave amplitude.

A wave generator comprising:

• quadrant means for inverting lower bits, a delta bit, and upper bits in response to a second bit;
• sign means for inverting a first bit in response to the delta bit to generate a sign bit;
• lower inverter means for inverting the lower bits in response to the delta bit;
• lookup means for generating a coarse value and a slope value for a value of the lower bits received from the quadrant means;
• coarse inverter means for inverting the coarse value in response to the delta bit;
• first logic means for generating product bits that represent a value of the slope value multiplied by the lower bits from the lower inverter means;
• second logic means for generating amplitude bits that represent a sum of the product bits and the coarse value from the coarse inverter means;
• wherein the sign bit indicates a polarity of the amplitude bits;
• and
• output means for outputting the sign bit and the amplitude bits as a wave function result.