Memory unit and method of operating the same
AssigneeSony Corporation
InventorWataru Otsuka
Life of this patent
Estimating the term…
Abstract
A memory unit includes memory cells each having a memory element and a transistor, word lines and first and second bit lines, and a drive section. In performing setting operation for a first memory element located on one word line and in performing resetting operation for a second memory element located on the one word line, the drive section applies a given word line electric potential to the one word line, and sets an electric potential of a bit line on a lower electric potential side out of the first and the second bit lines corresponding to the first memory element to a value higher than a value of an electric potential of a bit line on the lower electric potential side corresponding to the second memory element by an amount of given electric potential difference.
Claims20
A memory unit comprising:
- a plurality of memory cells that each have a memory element in which a resistance state is reversibly changed according to polarity of an applied voltage and a transistor for selecting the memory cell as a drive target;
- a plurality of word lines and a plurality of first and second bit lines, each connected to one of the plurality of memory cells;
- and
- a drive section that selects at least one of the plurality of memory cells as the drive target and selectively changes the resistance state of the memory element of the memory cell selected as the drive target between a low resistance state and a high resistance state by applying electric potentials to the word line and the first and the second bit lines connected to the memory cell selected as the drive target,
- wherein the drive section performs a setting operation to change the resistance state from the high resistance state to the low resistance state for a first memory element located on one word line and a resetting operation to change the resistance state from the low resistance state to the high resistance state for a second memory element located on the one word line by:
- applying a first potential P1 to the one word line,
- applying a second potential P2 to the first bit line corresponding to the first memory element,
- applying the first potential P1 to the second bit line corresponding to the first memory element,
- applying the first potential P1 to the first bit line corresponding to the second memory element,
- applying and a third potential P3 to the second bit line corresponding to the second memory element,
- wherein P1, P2, and P3 are set such that:
- P2=P3+ΔV, and
- P1≧P2,
- where ΔV is a non-zero number.
A memory unit comprising:
- a plurality of memory cells that respectively have a memory element in which resistance state is reversibly changed according to polarity of an applied voltage and a transistor for selecting a memory element as a drive target;
- a plurality of word lines and a plurality of first and second bit lines connected to the plurality of memory cells;
- and
- a drive section that selectively changes resistance state of the memory element as the drive target between low resistance state and high resistance state by applying a given electric potential to the word line and the first and the second bit lines,
- wherein in performing setting operation to change resistance state from the high resistance state to the low resistance state for a first memory element located on one word line and in performing resetting operation to change resistance state from the low resistance state to the high resistance state for a second memory element located on the one word line, the drive section applies a given word line electric potential to the one word line, and sets an electric potential of a bit line on a lower electric potential side out of the first and the second bit lines corresponding to the first memory element to a value higher than a value of an electric potential of a bit line on the lower electric potential side corresponding to the second memory element by an amount of given electric potential difference,
- wherein the drive section applies a given setting voltage for performing the setting operation between the first and the second bit lines corresponding to the first memory element, and applies a given resetting voltage for performing the resetting operation between the first and the second bit lines corresponding to the second memory element,
- wherein the given electric potential difference is an electric potential difference obtained by subtracting a setting electric potential set in performing the setting operation for the memory element from a resetting electric potential set in performing the resetting operation for the memory element, and
- wherein the given word line electric potential is the resetting electric potential.
A method of operating a memory unit that has a plurality of memory cells that each have a memory element in which a resistance state is reversibly changed according to a polarity of an applied voltage and a transistor for selecting the memory element as a drive target and a plurality of word lines and a plurality of first and second bit lines, each connected to one of the plurality of memory cells, the method comprising:
- performing a setting operation for a first memory element connected to a first word line of the plurality of word lines and a resetting operation for a second memory element connected to the first word line by:
- applying a first potential P1 to the first word line,
- applying a second potential P2 to the first bit line corresponding to the first memory element,
- applying the first potential P1 to the second bit line corresponding to the first memory element,
- applying the first potential P1 to the first bit line corresponding to the second memory element,
- applying and a third potential P3 to the second bit line corresponding to the second memory element,
- wherein P1 P2 and P3 are set such that:
- P2=P3+ΔV, and
- P1≧P2,
- where ΔV is a non-zero number.
A memory unit comprising:
- a plurality of memory cells that respectively have a memory element in which resistance state is reversibly changed according to polarity of an applied voltage and a transistor for selecting a memory element as a drive target;
- a plurality of resistance elements indicating a fixed resistance value;
- a plurality of word lines and a plurality of first and second bit lines connected to the plurality of memory cells;
- and
- a drive section that selectively changes resistance state of the memory element as the drive target between low resistance state and high resistance state by applying a given electric potential to the word line and the first and the second bit lines,
- wherein in the memory cell, the word line is connected to a gate of the transistor,
- the first bit line is connected to one of a source and a drain in the transistor with the resistance element in between, and
- the second bit line is connected to the other one of the source and the drain in the transistor with the memory element in between.
A method of operating a memory unit, wherein in operating a memory unit that includes a plurality of memory cells respectively having a memory element in which resistance state is reversibly changed according to polarity of an applied voltage and a transistor for selecting a memory element as a drive target, a plurality of resistance elements indicating a fixed resistance value, and a plurality of word lines and a plurality of first and second bit lines connected to the plurality of memory cells, in which in the memory cell, the word line is connected to a gate of the transistor, the first bit line is connected to one of a source and a drain in the transistor with the resistance element in between, and the second bit line is connected to the other one of the source and the drain in the transistor with the memory element in between,
- a given word line electric potential is applied to one word line,
- while an electric potential of a bit line on a lower electric potential side out of the first and the second bit lines corresponding to a first memory element located on the one word line is set to a value equal to that of an electric potential of a bit line on the lower electric potential side corresponding to a second memory element located on the one word line,
- a given setting voltage for performing setting operation is applied between the first and the second bit lines corresponding to the first memory element, and a given resetting voltage for performing resetting operation is applied between the first and the second bit lines corresponding to the second memory element, and thereby
- the setting operation to change resistance state from high resistance state to low resistance state is performed for the first memory element, and the resetting operation to change resistance state from the low resistance state to the high resistance state is performed for the second memory element.
A memory unit comprising:
- memory cells that each include a memory element in which a resistance state is reversibly changed according to polarity of an applied voltage and a transistor for selecting the memory element as a drive target;
- word lines, first bit lines, and second bit lines, each of the memory cells being connected to one of the word lines, one of the first bit lines, and one of the second bit lines;
- and
- a drive section that selects at least one of the memory cells as the drive target and selectively changes the resistance state of the memory element of the memory cell selected as the drive target between a low resistance state and a high resistance state by applying electric potentials to the word line and the first and second bit lines connected to the memory cell selected as the drive target,
- wherein the drive section performs a setting operation for a first memory element located on a first word line concurrently with performing a resetting operation for a second memory element located on the first word line by applying a first potential P1 to the first word line, and while the first potential P1 is applied to the first word line:
- applying the first potential P1 to the second bit line corresponding to the first memory element,
- applying the first potential P1 to the first bit line corresponding to the second memory element,
- applying and a third potential P3 to the second bit line corresponding to the second memory element,
- wherein P1, P2, and P3 are set such that:
- P2=P3+ΔV, and
- P1≧P2,
- where ΔV is a non-zero number.
Dependencies are inferred from the claim text.