# US 9,019,738 B2 · Memory device having sequentially cascading dices

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- Number: US 9,019,738 B2
- Document ID: US9019738B2
- Status: Granted
- Kind: B2
- Application number: 14/133,844
- Filed: 2013-12-19
- Published: 2015-02-26
- Granted: 2015-04-28
- Earliest claimed: 2013-08-23
- Assignees: Eorex Corporation
- Applicants: Eorex Corporation
- Inventors: Cheng-Lung Lin
- Web page: https://patentgrep.com/patent/US9019738B2

## CPC

- G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)}
- G11C 5/06: Arrangements for interconnecting storage elements electrically, e.g. by wiring
- G11C 5/063: {Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay}
- H10W 90/00: Package configurations
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A memory device is provided. The memory device is used for data transmission at around 1600 megahertz (MHz). A wire layout is used to sequentially cascade memory dices with greatly shortened distances between the wire layout and the memory dices. At the same time, distances between the wire layout and UA controllers are shortened as well for effectively simplifying the design of wires.

## Claims

### Claim 1

A memory device having sequentially cascading dices, comprising
a substrate;
a plurality of memory dices, said memory dices being located on at least one surface of said substrate, said memory dices having unit address (UA) controllers correspondingly arranged in array;
a wire layout, said wire layout using said UA controllers to sequentially cascade said memory dices;
a processing unit, said processing unit being located at an end of said wire layout; and
a reflective signal absorption unit, said reflective signal absorption unit being located at another end of said wire layout,
wherein said substrate has a plurality of penetrating hole; said memory dices are located on a surface of said substrate; said UA controllers are separately corresponding to said penetrating holes; said wire layout is located on another surface of said substrate to form an ‘Ω’ shape; and said UA controller is connected with said wire layout by a conducting wire through said corresponding penetrating hole.

### Claim 2 (depends on 1)

The memory device according to claim 1,
wherein said UA controller is a pin.

### Claim 3 (depends on 1)

The memory device according to claim 1,
wherein said wire layout is a bus.

### Claim 4 (depends on 1)

The memory device according to claim 1,
wherein said UA controllers of neighboring memory dices are corresponding to each other.

### Claim 5 (depends on 1)

The memory device according to claim 1,
wherein said reflective signal absorption unit is a resistance.

### Claim 6

A memory device having sequentially cascading dices, comprising a substrate;
a plurality of memory dices, said memory dices being located on at least one surface of said substrate, said memory dices having unit address (UA) controllers correspondingly arranged in array;
a wire layout, said wire layout using said UA controllers to sequentially cascade said memory dices;
a processing unit, said processing unit being located at an end of said wire layout; and
a reflective signal absorption unit, said reflective signal absorption unit being located at another end of said wire layout,
wherein said wire layout is directly obtained on a surface of said substrate to form an ‘Ω’ shape; and said memory dice is combined with said wire layout through said corresponding UA controller.