Electronic device, in particular for protection against electrostatic discharges, and method for protecting a component against electrostatic discharges

An electronic device, comprising:

• a first terminal;
• a second terminal;
• and
• electronic circuitry coupled between the first and second terminals, wherein the electronic circuitry comprises at least one block formed in a substrate and comprising an MOS transistor that has a first electrode, a second electrode, a gate and includes a parasitic bipolar transistor, the MOS transistor having its first electrode coupled to the first terminal, its second electrode coupled to the second terminal and also being configured to, in the presence of a current pulse between the first and second terminals, operate in a hybrid mode including an MOS-type operation in a below-threshold mode and an operation of the parasitic bipolar transistor, wherein
• the block further comprises a control circuit configured to, in the presence of a current pulse between the first and second terminals, apply a first non-zero voltage to the substrate of the MOS transistor and a second voltage below a threshold voltage to the gate of the MOS transistor, wherein the control circuit is configured to apply a first voltage below a limit voltage corresponding to a saturation substrate-source voltage of the parasitic bipolar transistor.

An electronic device, comprising:

• a first terminal;
• a second terminal;
• and
• electronic circuitry coupled between the first and second terminals, wherein the electronic circuitry comprises at least one block formed in a substrate and comprising an MOS transistor that has a first electrode, a second electrode, a gate and includes a parasitic bipolar transistor, the MOS transistor having its first electrode coupled to the first terminal, its second electrode coupled to the second terminal and also being configured to, in the presence of a current pulse between the first and second terminals, operate in a hybrid mode including an MOS-type operation in a below-threshold mode and an operation of the parasitic bipolar transistor, wherein the at least one block of the electronic circuitry comprises two cascode-connected blocks.

An electronic device, comprising:

• a first terminal;
• a second terminal;
• and
• electronic circuitry coupled between the first and second terminals, wherein the electronic circuitry comprises at least one block formed in a substrate and comprising an MOS transistor that has a first electrode, a second electrode, a gate and includes a parasitic bipolar transistor, the MOS transistor having its first electrode coupled to the first terminal, its second electrode coupled to the second terminal and also being configured to, in the presence of a current pulse between the first and second terminals, operate in a hybrid mode including an MOS-type operation in a below-threshold mode and an operation of the parasitic bipolar transistor, wherein the at least one block of the electronic circuitry comprises first and second identical blocks symmetrically coupled in series between the first terminal and the second terminal.

A protection device configured for protecting against electrostatic discharges, the device comprising:

• a first terminal;
• a second terminal, the first and second terminals configured to be connected to a component to be protected;
• and
• electronic circuitry disposed in a substrate and coupled between the first and second terminals, the electronic circuitry comprising at least one first block comprising an MOS transistor that has a gate coupled to the substrate without being directly coupled to the second terminal, a first electrode of the MOS transistor being coupled to the first terminal, and a second electrode of the MOS transistor being coupled to the second terminal, the electronic circuitry further comprising a first resistive element coupled between the substrate of the MOS transistor and the second terminal, wherein the electronic circuitry further comprises a diode having a first anode/cathode connected to the first terminal and a second anode/cathode connected to the second terminal.

A protection device configured for protecting against electrostatic discharges, the device comprising:

• a first terminal;
• a second terminal, the first and second terminals configured to be connected to a component to be protected;
• and
• electronic circuitry disposed in a substrate and coupled between the first and second terminals, the electronic circuitry comprising a first block comprising an MOS transistor that has a gate coupled to the substrate without being directly coupled to the second terminal, a first electrode of the MOS transistor being coupled to the first terminal, and a second electrode of the MOS transistor being coupled to the second terminal, the electronic circuitry further comprising a first resistive element coupled between the substrate of the MOS transistor and the second terminal, wherein
• the gate of the MOS transistor of the first block is not coupled to the second terminal, and
• the electronic circuitry further comprises a second block comprising an MOS transistor that has a gate coupled to a substrate of the transistor without being coupled to the first terminal, a first electrode coupled to the first terminal and a resistive element coupled between the substrate of the transistor and the first terminal, the first electrode of the MOS transistor of the first block being coupled to the first terminal via the MOS transistor of the second block, the MOS transistor of the second block having its second electrode coupled to the second terminal via the MOS transistor of the first block.

An input/output cell of an integrated circuit, comprising:

• an input/output pin,
• a first power supply terminal,
• a second power supply terminal,
• a first device coupled between the first power supply terminal and the input/output pin, the first device including first and second terminals and electronic circuitry coupled between the first power supply terminal and the input / output pin, the electronic circuitry comprising at least one block comprising an MOS transistor that has a first electrode, a second electrode, a gate and includes a parasitic bipolar transistor, the MOS transistor having its first electrode coupled to the first power supply terminal, its second electrode coupled to the input/output pin and also being configured to, in the presence of a current pulse between the first power supply terminal and the input/output pin, operate in a hybrid mode including an MOS-type operation in a below-threshold mode and an operation of the parasitic bipolar transistor;
• a second device coupled between the input/output pin and the second power supply terminal, the second device including third and fourth terminals and second electronic circuitry coupled between the input/output pin and the second power supply terminal, the second electronic circuitry comprising at least one block comprising an MOS transistor that has a first electrode, a second electrode, a gate and includes a parasitic bipolar transistor, the MOS transistor having its first electrode coupled to the input/output pin, its second electrode coupled to the second power supply terminal and also being configured to, in the presence of a current pulse between the first and second power terminals, operate in a hybrid mode including an MOS-type operation in a below-threshold mode and an operation of the parasitic bipolar-transistor;
• and
• a third device coupled between the first power supply terminal and the second power supply terminal, the third device including fifth and sixth terminals and third electronic circuitry coupled between the first and second power terminals, the third electronic circuitry comprising at least one block comprising an MOS transistor that has a first electrode, a second electrode, a gate and includes a parasitic bipolar transistor, the MOS transistor having its first electrode coupled to the first power supply terminal, its second electrode coupled to the second power supply terminal and also being configured to, in the presence of a current pulse between the first and second power supply terminals, operate in a hybrid mode including an MOS-type operation in a below-threshold mode and an operation of the parasitic bipolar transistor.