# US 9,018,024 B2 · Creating extremely thin semiconductor-on-insulator (ETSOI) having substantially uniform thickness

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- Number: US 9,018,024 B2
- Document ID: US9018024B2
- Status: Granted
- Kind: B2
- Application number: 12/603,668
- Filed: 2009-10-22
- Published: 2011-04-28
- Granted: 2015-04-28
- Earliest claimed: 2009-10-22
- Assignees: International Business Machines Corporation
- Applicants: Nathaniel C. Berliner; Kangguo Cheng; Jason E. Cummings; Toshiharu Furukawa; Jed H. Rankin; Robert R. Robison; William R. Tonti
- Inventors: Nathaniel C. Berliner; Kangguo Cheng; Jason E. Cummings; Toshiharu Furukawa; Jed H. Rankin; Robert R. Robison; William R. Tonti
- Web page: https://patentgrep.com/patent/US9018024B2

## CPC

- H10P 90/1906: {Preparing SOI wafers}
- H10P 52/402: {of semiconductor materials}
- H10P 74/203: {Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects}
- H10P 74/23: {characterised by multiple measurements, corrections, marking or sorting processes}
- H10W 10/181: {Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers}
- Y10S 438/959: Mechanical polishing of wafer
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- Y10S: TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS

## Abstract

An extremely thin semiconductor-on-insulator (ETSOI) wafer is created having a substantially uniform thickness by measuring a semiconductor layer thickness at a plurality of selected points on a wafer; determining a removal thickness to be removed at each of the plurality of selected points such that removal of the removal thickness results in a substantially uniform within-wafer semiconductor layer thickness; implanting a species into the wafer at each of the plurality of selected points with at least one of a dose level and an energy level based on the removal thickness for the respective point; and polishing the semiconductor layer to thin the semiconductor layer.

## Claims

### Claim 1

A method comprising:
measuring a semiconductor layer thickness at a plurality of selected points on a wafer;
determining a removal thickness to be removed at each of the plurality of selected points, wherein the removal thickness is different for each of the plurality of selected points and comprises the amount required to be removed at each selected point in order to result in a substantially uniform within-wafer semiconductor layer thickness;
implanting a species into the wafer at each of the plurality of selected points with a different dose level and a different energy level for each of the plurality of selected points based on the removal thickness for each of the plurality of selected points; and
polishing the semiconductor layer to thin the semiconductor layer, wherein the implanting results in a different polishing rate for each of the plurality of selected points resulting in a substantially uniform thickness of the semiconductor layer.

### Claim 2 (depends on 1)

The method of claim 1, wherein the species includes an inert gas.

### Claim 3 (depends on 1)

The method of claim 1, wherein the species is selected from the group consisting of: germanium (Ge), silicon (Si), argon (Ar), xenon (Xe).

### Claim 4 (depends on 1)

The method of claim 1, wherein the thinning results in the semiconductor layer having a thickness of no more than approximately 40 angstroms.

### Claim 5 (depends on 1)

The method of claim 1, wherein the semiconductor layer is a semiconductor-on-insulator (SOI) layer of a SOI wafer.

### Claim 6 (depends on 1)

The method of claim 1, wherein the implanting includes using an infusion gas cluster ion implanter system.

### Claim 7 (depends on 1)

The method of claim 1, wherein the implanting includes using a spot beam ion implanter system.

### Claim 8 (depends on 1)

The method of claim 1, wherein the polishing includes performing chemical mechanical polishing (CMP).

### Claim 9 (depends on 1)

The method of claim 1, wherein the measuring includes scanning the wafer using an interferometry-based device.

### Claim 10 (depends on 1)

The method of claim 1, further comprising: generating a topographical map indicating thicknesses across the wafer based on the measuring.

### Claim 11 (depends on 1)

The method of claim 1, wherein the determining includes calculating the removal thickness for each of the selected points by subtracting the measured thickness at each point from a desired thickness.

### Claim 12 (depends on 1)

The method of claim 1, wherein the removal thickness is expressed as a topographical map indicating removal thickness across the wafer.