Adaptive redundancy in three dimensional memory
AssigneeSanDisk Technologies LLC
InventorXinde Hu
Life of this patent
Estimating the term…
Abstract
In a three-dimensional nonvolatile memory, physical layers are zoned according to expected error rate. Different redundancy schemes are applied to different zones so that a high degree of redundancy is applied to a zone with a high expected error rate and a low degree of redundancy is applied to a zone with a low expected error rate.
Claims17
A method of operating a three-dimensional nonvolatile memory that is monolithically formed in a plurality of physical levels of memory cells disposed above a substrate, memory cells in the plurality of physical levels connected in series to foim vertical NAND strings, comprising:
- categorizing the plurality of physical levels into at least a first category of physical levels and a second category of physical levels according to expected error rate, the first category of physical levels having a first expected error rate, the second category of physical levels having a second expected error rate that is less than the first expected error rate;
- performing a redundancy calculation for data in the first category of physical levels, across N blocks of the three-dimensional nonvolatile memory, to generate first redundant data;
- storing the first redundant data in a redundant block in the three-dimensional nonvolatile memory;
- performing a redundancy calculation for data in the second category of physical levels, across N+X blocks of the three-dimensional nonvolatile memory, to generate second redundant data;
- and
- storing the second redundant data in the redundant block.
A three-dimensional nonvolatile NAND memory system comprising:
- a three-dimensional nonvolatile NAND memory that is monolithically formed in a plurality of physical levels of memory cells disposed above a substrate, the plurality of physical levels including high risk physical levels in which there is a high risk of bad bits and low risk physical levels in which there is a low risk of bad bits;
- a plurality of memory hole structures extending vertically through the plurality of physical levels to connect memory cells of the plurality of physical levels into vertical NAND strings, the plurality of memory hole structures having small diameters in the high risk physical levels and having large diameters in the low risk physical levels;
- and
- a redundancy circuit that is configured to generate redundant data with different degrees of redundancy for high risk physical levels and low risk physical levels.
A method of operating a three-dimensional nonvolatile memory that is monolithically formed in a plurality of physical levels of memory cells disposed above a substrate, memory cells in the plurality of physical levels connected in series to form vertical NAND strings, comprising:
- categorizing the plurality of physical levels into at least a first category of physical levels and a second category of physical levels according to expected error rate, the first category of physical levels having a first expected error rate, the second category of physical levels having a second expected error rate that is less than the first expected error rate, physical levels of the first category being physically located between physical levels of the second category and the substrate;
- performing a first Exclusive OR (XOR) calculation for data in the first category of physical levels, across N blocks of the three-dimensional nonvolatile memory, to generate first redundant data;
- storing the first redundant data in the three-dimensional nonvolatile memory;
- performing a second XOR calculation for data in the second category of physical levels, across N+X blocks of the three-dimensional nonvolatile memory, to generate second redundant data;
- and
- storing the second redundant data in the three-dimensional nonvolatile memory.
A three-dimensional nonvolatile NAND memory system comprising:
- a three-dimensional nonvolatile NAND memory that is monolithically formed in a plurality of physical levels of memory cells disposed above a substrate, the plurality of physical levels including high risk physical levels in which there is a high risk of bad bits and low risk physical levels in which there is a low risk of bad bits;
- a plurality of memory hole structures extending vertically through the plurality of physical levels to connect memory cells of the plurality of physical levels into vertical NAND strings, the plurality of memory hole structures having small diameters in the high risk physical levels and having large diameters in the low risk physical levels;
- an Error Correction Code (ECC) circuit that is configured to encode data prior to storage in the three-dimensional nonvolatile NAND memory, configured to decode data that is read from the three-dimensional nonvolatile NAND memory, and configured to identify when data that is read from the three-dimensional NAND memory is uncorrectable;
- and
- an XOR circuit that is configured to generate XOR data with different degrees of redundancy for high risk physical levels and low risk physical levels, and configured to regenerate a portion of data from XOR data when the ECC circuit identifies the portion of data as uncorrectable.
Dependencies are inferred from the claim text.