Circuits for improving linearity of metal oxide semiconductor (MOS) transistors

A circuit for improving linearity of a Metal Oxide Semiconductor (MOS) transistor comprising a gate, a source and a drain, the circuit comprising:

• an averaging circuit configured to provide a signal at the gate in response to signals at the drain and the source, the averaging circuit comprising:
• a first MOS circuit configured to be coupled between the drain and the gate, and
• a second MOS circuit configured to be coupled between the source and the gate;
• and
• one or more current sources coupled with the gate, the one or more current sources configured to vary currents in the first and second MOS circuits so as to vary a voltage at the gate and thereby vary a resistance of the MOS transistor, wherein the one or more current sources comprises a current source coupled between a power supply and the gate and a current sink coupled between the gate and a substrate voltage.

A circuit, comprising:

• an averaging circuit configured to be coupled with a Metal Oxide Semiconductor (MOS) transistor, the MOS transistor comprising a gate, a source and a drain, and the averaging circuit configured to provide an average of signals at the drain and the source to the gate, the averaging circuit comprising:
• a first MOS circuit coupled between a first node and a second node, the first node configured to be coupled with the drain, the second node configured to be coupled with the gate, and the first MOS circuit configured to provide a signal at the second node in response to a signal at the first node, wherein the first MOS circuit comprises:
• a source follower MOS circuit comprising:
• a first PMOS transistor having a gate node coupled with the first node, and
• a first current source coupled between a power supply and a source node of the first PMOS transistor;
• and
• a first resistor coupling the source node of the first PMOS transistor with the second node,
• a first capacitor coupled in parallel with the first MOS circuit between the first node and the second node,
• a second MOS circuit coupled between a third node and the second node, the third node configured to be coupled with the source, and the second MOS circuit configured to provide a signal at the second node that is responsive to a signal at the third node, and
• a second capacitor coupled in parallel with the second MOS circuit between the third node and the second node,
• wherein the first MOS circuit and the second MOS circuit are configured to average the signals at the drain and the source at a first signal frequency, and wherein the first capacitor and the second capacitor are configured to average the signals at the drain and the source at a second signal frequency, the second signal frequency being higher than the first signal frequency;
• and
• one or more current sources coupled with the second node, the one or more current sources configured to vary currents in the first and second MOS circuits so as to vary a voltage at the second node and thereby vary a voltage at the gate for varying a resistance of the MOS transistor.

A circuit, comprising:

• an averaging circuit configured to be coupled with a Metal Oxide Semiconductor (MOS) transistor, the MOS transistor comprising a gate, a source and a drain, and the averaging circuit configured to provide an average of signals at the drain and the source to the gate, the averaging circuit comprising:
• a first MOS circuit coupled between a first node and a second node, the first node configured to be coupled with the drain, the second node configured to be coupled with the gate, and the first MOS circuit configured to provide a signal at the second node in response to a signal at the first node,
• a first capacitor coupled in parallel with the first MOS circuit between the first node and the second node,
• a second MOS circuit coupled between a third node and the second node, the third node configured to be coupled with the source, and the second MOS circuit configured to provide a signal at the second node that is responsive to a signal at the third node, and
• a second capacitor coupled in parallel with the second MOS circuit between the third node and the second node;
• and
• one or more current sources coupled with the second node, the one or more current sources configured to vary currents in the first and second MOS circuits so as to vary a voltage at the second node and thereby vary a voltage at the gate for varying a resistance of the MOS transistor, wherein the one or more current sources comprises a current source coupled between a power supply and the second node and a current sink coupled between the second node and a substrate voltage.

A Metal Oxide Semiconductor (MOS) resistor, comprising:

• a MOS transistor having a drain, a source and a gate, configured to operate in linear region as a resistor;
• an averaging circuit configured to provide a signal at the gate in response to signals at the drain and the source, the averaging circuit comprising:
• a first MOS circuit coupled between the drain and the gate, wherein the first MOS circuit comprises:
• a source follower MOS circuit comprising:
• a first PMOS transistor having a gate node coupled with the drain of the MOS transistor, and
• a first current source coupled between a power supply and a source node of the first PMOS transistor;
• and
• a first resistor coupling the source node of the first PMOS transistor with the gate of the MOS transistor,
• a first capacitor coupled in parallel with the first MOS circuit between the drain and the gate,
• a second MOS circuit coupled between the source and the gate, and
• a second capacitor coupled in parallel with the second MOS circuit between the source and the gate;
• and
• one or more current sources coupled with the gate, the one or more current sources configured to vary currents in the first MOS circuit and the second MOS circuit so as to vary a voltage at the gate and thereby vary a resistance of the MOS transistor.

A Metal Oxide Semiconductor (MOS) resistor, comprising:

• a MOS transistor having a drain, a source and a gate, configured to operate in linear region as a resistor;
• an averaging circuit configured to provide a signal at the gate in response to signals at the drain and the source, the averaging circuit comprising:
• a first MOS circuit coupled between the drain and the gate,
• a first capacitor coupled in parallel with the first MOS circuit between the drain and the gate,
• a second MOS circuit coupled between the source and the gate, wherein the second MOS circuit comprises:
• a source follower MOS circuit comprising:
• a second PMOS transistor having a gate node configured to be coupled with the source of the MOS transistor, and
• a second current source coupled with between the power supply and a source node of the second PMOS transistor;
• and
• a second resistor coupling the source node of the second PMOS transistor with the gate of the MOS transistor, and
• a second capacitor coupled in parallel with the second MOS circuit between the source and the gate;
• and
• one or more current sources coupled with the gate, the one or more current sources configured to vary currents in the first MOS circuit and the second MOS circuit so as to vary a voltage at the gate and thereby vary a resistance of the MOS transistor.