# US 9,006,899 B2 · Layer stack

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- Number: US 9,006,899 B2
- Document ID: US9006899B2
- Status: Granted
- Kind: B2
- Application number: 13/716,017
- Filed: 2012-12-14
- Published: 2014-06-19
- Granted: 2015-04-14
- Earliest claimed: 2012-12-14
- Assignees: Infineon Technologies AG
- Applicants: Infineon Technologies AG
- Inventors: Paul Ganitzer; Kurt Matoy; Martin Sporn; Mark Harrison
- Web page: https://patentgrep.com/patent/US9006899B2

## CPC

- H10W 70/66: Conductive materials thereof
- H10W 72/90: Bond pads, in general
- H10P 14/40: of conductive or resistive materials
- H10W 72/019: {of bond pads}
- H10W 72/01955: {by using masks}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/352: {comprising metals or metalloids, e.g. solders}
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

In one embodiment method, a first Ti based layer is deposited on the substrate. An intermediate Al based layer is deposited on the first layer, a second NiV based layer is deposited on the intermediate layer, and a third Ag based layer is deposited on the second layer. The layer stack is tempered in such a way that at least one inter-metallic phase is formed between at least two metals of the group containing Ti, Al, Ni and V.

## Claims

### Claim 1

A layer stack, comprising:
a first layer, wherein the first layer contains Ti and has a thickness in a range from 100 nm to 400 nm;
an intermediate layer disposed over the first layer, wherein the intermediate layer contains Al and has a thickness in a range from 30 nm to 50 nm, wherein the Al is partly converted to an intermetallic phase with a metal from the group consisting of Ti, Ni and V;
a second layer disposed over the intermediate layer, wherein the second layer contains NiV and has a thickness in a range from 200 nm to 400 nm; and
a third layer disposed over the second layer, wherein the third layer contains Ag and has a thickness in a range from 200 nm to 600 nm.

### Claim 2 (depends on 1)

An electronic module according to claim 1, further comprising a substrate, wherein the layer stack is disposed on the substrate.

### Claim 3 (depends on 2)

The electronic module according to claim 2, further comprising at least one electronic device in or on the substrate.

### Claim 4 (depends on 3)

The electronic module according to claim 3, wherein the electronic device comprises one or more of a power transistor, a MOS transistor, an SFET transistor, a vertical transistor, and an Insulated Gate Bipolar (IGB) transistor.

### Claim 5 (depends on 2)

The electronic module according to claim 2, wherein the layer stack is arranged over only predetermined portions of a main surface of the substrate.

### Claim 6 (depends on 5)

The electronic module according to claim 5, wherein the predetermined portions comprise electrical contact terminals of an electrical device.

### Claim 7 (depends on 2)

The electronic module according to claim 2, wherein the layer stack is arranged over an entire main face of the substrate.