# US 9,006,887 B2 · Forming sacrificial composite materials for package-on-package architectures and structures formed thereby

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- Number: US 9,006,887 B2
- Document ID: US9006887B2
- Status: Granted
- Kind: B2
- Application number: 12/380,957
- Filed: 2009-03-04
- Published: 2010-09-09
- Granted: 2015-04-14
- Earliest claimed: 2009-03-04
- Assignees: Intel Corporation
- Applicants: Rajasekaran Swaminathan; Leonel Arana; Yoshihiro Tomita; Yosuke Kanaoka
- Inventors: Rajasekaran Swaminathan; Leonel Arana; Yoshihiro Tomita; Yosuke Kanaoka
- Web page: https://patentgrep.com/patent/US9006887B2

## CPC

- H05K 3/3485: Application of solder paste, slurry or powder (using printing techniques to form the desired conductive pattern of the printed circuit by applying conductive material H05K3/12)
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/69: Insulating materials thereof
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 74/131: {the semiconductor body being only partially enclosed}
- H10W 90/00: Package configurations
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H05K 3/3452: Solder masks
- H05K 2203/043: Reflowing of solder coated conductors, not during connection of components, e.g. reflowing solder paste
- H05K 2203/083: Evaporation or sublimation of a compound, e.g. gas bubble generating agent
- H05K 2203/1476: Same or similar kind of process performed in phases, e.g. coarse patterning followed by fine patterning
- H10W 72/01: {Manufacture or treatment}
- H10W 72/01257: {by reflowing}
- H10W 72/07252: {changes in structures or sizes}
- H10W 72/221: {Structures or relative sizes}
- H10W 72/90: Bond pads, in general
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Methods of forming a microelectronic packaging structure are described. Those methods may include forming a solder paste comprising a sacrificial polymer on a substrate, curing the solder paste below a reflow temperature of the solder to form a solid composite hybrid bump on the conductive pads, forming a molding compound around the solid composite hybrid bump, and reflowing the hybrid bump, wherein the sacrificial polymer is substantially decomposed.

## Claims

### Claim 1

A structure comprising:
a solder disposed on a conductive pad of a substrate;
a polymer disposed in contact with a surface of the solder;
a molding compound disposed on the substrate and spaced apart from the surface of the solder;
wherein the polymer has a thermal decomposition temperature that is no greater than a reflow temperature of the solder; and
wherein the surface of the solder is separated from the molding compound by the polymer.

### Claim 2 (depends on 1)

The structure of claim 1, wherein the polymer comprises a curable polymer, and has a cure temperature that is less than a reflow temperature of the solder.

### Claim 3 (depends on 1)

The structure of claim 1, wherein the polymer comprises a polynorbornene material.

### Claim 4 (depends on 1)

The structure of claim 1, wherein the polymer comprises a polycarbonate material.

### Claim 5 (depends on 1)

The structure of claim 1, wherein the polymer has a density that is lower than that of the solder.