# US 9,006,860 B2 · Metal gate features of semiconductor die > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,006,860 B2 - Document ID: US9006860B2 - Status: Granted - Kind: B2 - Application number: 13/312,306 - Filed: 2011-12-06 - Published: 2013-06-06 - Granted: 2015-04-14 - Earliest claimed: 2011-12-06 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Harry-Hak-Lay Chuang; Ming Zhu - Inventors: Harry-Hak-Lay Chuang; Ming Zhu - Web page: https://patentgrep.com/patent/US9006860B2 ## CPC - H10D 84/811: {Combinations of field-effect devices and one or more diodes, capacitors or resistors} - H10D 1/47: Resistors having no potential barriers - H10D 64/013: {of electrodes having a conductor capacitively coupled to a semiconductor by an insulator} - H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes} - H10D 64/517: {characterised by the conducting layers} - H10D 64/665: {the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum (having lateral variation H10D64/671)} - H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)} - H10D 84/0177: {the gate conductors having different materials or different implants} - H10D 84/0179: {the gate conductors having different shapes or dimensions} - H10D 84/0188: {Manufacturing their isolation regions} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10D 84/817: {Combinations of field-effect devices and resistors only} - H10D 84/85: Complementary IGFETs, e.g. CMOS - H10D 89/10: Integrated device layouts - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A CMOS semiconductor die comprises a substrate; an insulation layer over a major surface of the substrate; a plurality of P-metal gate areas formed within the insulation layer collectively covering a first area of the major surface; a plurality of N-metal gate areas formed within the insulation layer collectively covering a second area of the major surface, wherein a first ratio of the first area to the second area is equal to or greater than 1; a plurality of dummy P-metal gate areas formed within the insulation layer collectively covering a third area of the major surface; and a plurality of dummy N-metal gate areas formed within the insulation layer collectively covering a fourth area of the major surface, wherein a second ratio of the third area to the fourth area is substantially equal to the first ratio. ## Claims ### Claim 1 A CMOS semiconductor die comprising: a substrate; an insulation layer over a major surface of the substrate; a plurality of P-metal gate areas within the insulation layer collectively covering a first area of the major surface within a first device region over the major surface; a plurality of N-metal gate areas within the insulation layer collectively covering a second area of the major surface within the first device region; a plurality of dummy P-metal gate areas within the insulation layer collectively covering a third area of the major surface within a second device region over the major surface; and a plurality of dummy N-metal gate areas within the insulation layer collectively covering a fourth area of the major surface within the second device region; wherein the N-metal gate areas of the plurality of N-metal gate areas within the first device region individually differ in size compared to the P-metal gate areas of the plurality P-metal gate areas within the first device region, and the dummy P-metal gate areas of the plurality of dummy P-metal gate areas within the second device region are individually uniform in size with respect to the dummy N-metal gate areas of the plurality of dummy N-metal gate areas within the second device region. ### Claim 2 (depends on 1) The CMOS semiconductor die of claim 1, wherein a first ratio of the first area to the second area is from 1 to 3. ### Claim 3 (depends on 2) The CMOS semiconductor die of claim 2, wherein a second ratio of the third area to the fourth area is from 1 to 3. ### Claim 4 (depends on 1) The CMOS semiconductor die of claim 1, wherein the dummy P-metal gate areas of the plurality of dummy P-metal gate areas are similar in shape with respect to one another. ### Claim 5 (depends on 1) The CMOS semiconductor die of claim 1, wherein the dummy N-metal gate areas of the plurality of dummy N-metal gate areas are similar in shape with respect to one another. ### Claim 6 (depends on 1) The CMOS semiconductor die of claim 1, wherein the dummy P-metal gate areas of the plurality of dummy P-metal gate areas have a similar shape compared to the dummy N-metal gate areas of the plurality of dummy N-metal gate areas. ### Claim 7 (depends on 1) The CMOS semiconductor die of claim 1, wherein one dummy N-metal gate area of the plurality of dummy N-metal gate areas is between two dummy P-metal gate areas of the plurality of dummy P-metal gate areas. ### Claim 8 (depends on 1) The CMOS semiconductor die of claim 1, wherein one dummy P-metal gate area of the plurality of dummy P-metal gate areas is between two dummy N-metal gate areas of the plurality of dummy N-metal gate areas. ### Claim 9 (depends on 1) The CMOS semiconductor die of claim 1, wherein one dummy N-metal gate area of the plurality of dummy N-metal gate areas is between one dummy P-metal gate area of the plurality of dummy P-metal gate areas and one P-metal gate area of the plurality of P-metal gate areas. ### Claim 10 (depends on 1) The CMOS semiconductor die of claim 1, wherein one dummy P-metal gate area of the plurality of dummy P-metal gate areas is between one dummy N-metal gate area of the plurality of dummy N-metal gate areas and one N-metal gate area of the plurality of N-metal gate areas. ### Claim 11 (depends on 1) The CMOS semiconductor die of claim 1, wherein the dummy P-metal gate areas of the plurality of dummy P-metal gate areas comprise one or more of TiN, WN, TaN, or Ru. ### Claim 12 (depends on 1) The CMOS semiconductor die of claim 1, wherein the dummy N-metal gate areas of the plurality of dummy N-metal gate areas comprise one or more of Ti, Ag, Al, TiAl, TiAlN, TaC, TaCN, TaSiN, Mn, or Zr. ### Claim 13 (depends on 3) The CMOS semiconductor die of claim 3, further comprising: a plurality of resistor areas within the insulation layer collectively covering a fifth area of the major surface; a plurality of resistor contacts within the insulation layer; and a plurality of dummy resistor areas formed within the insulation layer collectively covering a sixth area of the major surface, wherein the resistor areas of the plurality of resistor areas comprise poly-silicon, and the resistor contacts of the plurality of resistor contacts comprise a third metal material. ### Claim 14 (depends on 13) The CMOS semiconductor die of claim 13, wherein a third ratio of the fifth area to a sum of the first area and second area is less than 0.05. ### Claim 15 (depends on 14) The CMOS semiconductor die of claim 14, wherein a fourth ratio of the sixth area to a sum of the third area and fourth area is less than 0.05. ### Claim 16 (depends on 13) The CMOS semiconductor die of claim 13, wherein the dummy resistor areas of the plurality of dummy resistor areas comprise poly-silicon. ### Claim 17 A CMOS semiconductor die comprising: a substrate; an insulation layer over a major surface of the substrate; a plurality of P-metal gate areas within the insulation layer collectively covering a first area of the major surface within a first device region over the major surface; a plurality of N-metal gate areas within the insulation layer collectively covering a second area of the major surface within the first device region; a plurality of dummy P-metal gate areas within the insulation layer collectively covering a third area of the major surface within a second device region over the major surface; and a plurality of dummy N-metal gate areas within the insulation layer collectively covering a fourth area of the major surface within the second device region, wherein a first ratio of the first area to the second area is equal to or greater than 1, and a second ratio of the third area to the fourth area is substantially equal to the first ratio. ### Claim 18 (depends on 17) The CMOS semiconductor die of claim 17, wherein the N-metal gate areas of the plurality of N-metal gate areas within the first device region individually differ in shape compared to the P-metal gate areas of the plurality P-metal gate areas within the first device region, and the dummy P-metal gate areas of the plurality of dummy P-metal gate areas within the second device region are individually uniform in shape with respect to the dummy N-metal gate areas of the plurality of dummy N-metal gate areas within the second device region. ### Claim 19 A CMOS semiconductor die comprising: a substrate; a plurality of P-metal gate areas over the substrate within a first device region; a plurality of N-metal gate areas over substrate within the first device region; a plurality of dummy P-metal gate areas over the substrate within a second device region, the second device region being different from the first device region; and a plurality of dummy N-metal gate areas over the substrate within the second device region; wherein a surface area of the first device region is larger than the second device region, N-metal gate areas of the plurality of N-metal gate areas within the first device region individually differ in size compared to the dummy N-metal gate areas of the plurality of dummy N-metal gate areas within the second device region, and the P-metal gate areas of the plurality P-metal gate areas within the first device region individually differ in size compared to the dummy P-metal gate areas of the plurality of dummy P-metal gate areas within the second device region. ### Claim 20 (depends on 19) The CMOS semiconductor die of claim 19, wherein the dummy P-metal gate areas of the plurality of dummy P-metal gate areas within the second device region are individually uniform in size with respect to the dummy N-metal gate areas of the plurality of dummy N-metal gate areas within the second device region.