# US 9,006,839 B2 · Semiconductor device

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- Number: US 9,006,839 B2
- Document ID: US9006839B2
- Status: Granted
- Kind: B2
- Application number: 14/261,970
- Filed: 2014-04-25
- Published: 2014-11-27
- Granted: 2015-04-14
- Earliest claimed: 2013-05-23
- Assignees: Toyota Jidosha Kabushiki Kaisha
- Applicants: Toyota Jidosha Kabushiki Kaisha
- Inventors: Tadashi Misumi
- Web page: https://patentgrep.com/patent/US9006839B2

## CPC

- H10D 12/441: {Vertical IGBTs}
- H10D 12/481: {having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs}
- H10D 62/109: {Reduced surface field [RESURF] PN junction structures}
- H10W 40/228: {the projecting parts being wire-shaped or pin-shaped}
- H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

In a semiconductor substrate of a semiconductor device, a drift layer, a body layer, an emitter layer, and a trench gate electrode are formed. When the semiconductor substrate is viewed in a plane manner, the semiconductor substrate is divided into a first region covered with a heat dissipation member, and a second region not covered with the heat dissipation member. A density of trench gate electrodes in the first region is equal to a density of trench gate electrodes in the second region. A value obtained by dividing an effective carrier amount of channel parts formed in the first region by an area of the first region is larger than a value obtained by dividing an effective carrier amount of channel parts formed in the second region by an area of the second region.

## Claims

### Claim 1

A semiconductor device comprising:
a semiconductor substrate;
a top surface electrode making contact with a top surface of the semiconductor substrate;
a bottom surface electrode making contact with a bottom surface of the semiconductor substrate; and
a heat dissipation member disposed above the top surface electrode, wherein:
the semiconductor substrate includes
a drift layer having a first conductivity type,
a body layer having a second conductivity type, the body layer making contact with a top surface of the drift layer,
a first semiconductor layer having the first conductivity type, the first semiconductor layer making contact with a top surface of the body layer, isolated from the drift layer by the body layer, exposed on the top surface of the semiconductor substrate, and making ohmic contact with the top surface electrode,
a second semiconductor layer having the second conductivity type, the second semiconductor layer making contact with the top surface of the body layer, isolated from the drift layer by the body layer, exposed on the top surface of the semiconductor substrate, and making ohmic contact with the top surface electrode,
trench gate electrodes disposed in respective gate trenches, the respective gate trenches penetrating through the body layer from the top surface of the semiconductor substrate to reach the drift layer, and
a gate insulating film disposed between each of the trench gate electrodes and a wall surface of a corresponding one of the gate trenches;
when the semiconductor substrate is viewed in a plane manner, each of the trench gate electrodes includes a first part and a second part, the first part being opposite to the first semiconductor layer via the gate insulating film, and the second part being opposite to the second semiconductor layer via the gate insulating film;
channel parts are formed in parts of the body layer which are opposite to the first parts of the trench gate electrodes;
when the semiconductor substrate is viewed in a plane manner, the semiconductor substrate is divided into a first region covered with the heat dissipation member, and a second region not covered with the heat dissipation member;
a density of the trench gate electrodes in the first region is equal to a density of the trench gate electrodes in the second region; and
a value obtained by dividing an effective carrier amount of the channel parts formed in the first region by an area of the first region is larger than a value obtained by dividing an effective carrier amount of the channel parts formed in the second region by an area of the second region.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein:
a first conductivity impurity concentration of the first semiconductor layer in the first region is equal to a first conductivity impurity concentration of the first semiconductor layer in the second region; and
when the semiconductor substrate is viewed in the plane manner, a value obtained by dividing an area of the channel parts formed in the first region by the area of the first region is larger than a value obtained by dividing an area of the channel parts formed in the second region by the area of the second region.

### Claim 3 (depends on 2)

The semiconductor device according to claim 2, wherein:
the semiconductor substrate includes a main part, and a sense part configured to detect a current flowing through the main part;
each of the main part and the sense part includes the drift layer, the body layer, the first semiconductor layer, the second semiconductor layer, and the trench gate electrodes; and
the sense part is disposed in the second region.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, wherein
a first conductivity impurity concentration of the first semiconductor layer in the first region is larger than a first conductivity impurity concentration of the first semiconductor layer in the second region.