# US 9,006,823 B2 · Semiconductor device and method of manufacturing semiconductor device

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- Number: US 9,006,823 B2
- Document ID: US9006823B2
- Status: Granted
- Kind: B2
- Application number: 14/166,031
- Filed: 2014-01-28
- Published: 2014-07-31
- Granted: 2015-04-14
- Earliest claimed: 2013-01-31
- Assignees: Toyota Jidosha Kabushiki Kaisha
- Applicants: Shinya Yamazaki
- Inventors: Shinya Yamazaki
- Web page: https://patentgrep.com/patent/US9006823B2

## CPC

- H10P 32/00: Diffusion of dopants within, into or out of wafers, substrates or parts of devices (during formation of materials H10P14/00)
- H10D 12/038: {having a recessed gate, e.g. trench-gate IGBTs}
- H10D 12/481: {having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs}
- H10D 30/0297: {using recessing of the gate electrodes, e.g. to form trench gate electrodes}
- H10D 30/665: {having edge termination structures}
- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D 62/051: {Forming charge compensation regions, e.g. superjunctions}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 62/106: {having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions}
- H10D 62/111: {Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures}
- H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device includes: a semiconductor substrate formed with an element region; a first conductive type first region formed in the element region and located on a surface side of the semiconductor substrate; a second conductive type second region located in a deeper position than the first region in the element region and contacting the first region; a first conductive type third region located in a deeper position than the second region in the element region, contacting the second region, and separated from the first region by the second region; and a gate disposed in a trench extending from the surface to reach the third region, and contacting a range of the second region via the insulation film. A thickness of the second region in a depth direction is gradually increased from the peripheral part of the element region to the central part thereof

## Claims

### Claim 1

A semiconductor device comprising:
a semiconductor substrate formed with an element region;
a first conductive type first region that is formed in the element region and located on a surface side of the semiconductor substrate;
a second conductive type second region that is located in a deeper position than the first region in the element region and contacts the first region;
a first conductive type third region that is located in a deeper position than the second region in the element region, contacts the second region, and is separated from the first region by the second region; and
a gate that is disposed in a trench extending from the surface of the semiconductor substrate to reach the third region and contacts a range of the second region that separates the first region from the third region via an insulation film, wherein
a thickness of the second region in a depth direction is gradually increased from a peripheral part of the element region to a central part of the element region.

### Claim 2 (depends on 1)

A method of manufacturing the semiconductor device according to claim 1, comprising:
forming a resist mask having plural openings that are disposed at intervals from each other in a surface of the semiconductor substrate; and
introducing a second conductive impurity into a depth for forming a range of the semiconductor substrate's second region that is exposed from the plural openings after formation of the resist mask, wherein
an area of each of the openings of the resist mask is gradually increased from the peripheral part of the element region to the central part.

### Claim 3 (depends on 2)

The method of manufacturing the semiconductor device according to claim 2 further comprising:
introducing a first conductive impurity to a depth for forming a range of the semiconductor substrate's first region that is exposed from the plural openings after the formation of the resist mask.