# US 9,006,742 B2 · Thin film transistor array panel

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- Number: US 9,006,742 B2
- Document ID: US9006742B2
- Status: Granted
- Kind: B2
- Application number: 13/952,059
- Filed: 2013-07-26
- Published: 2013-11-21
- Granted: 2015-04-14
- Earliest claimed: 2011-02-07
- Assignees: Samsung Display Co., Ltd.
- Applicants: Samsung Display Co., Ltd.
- Inventors: Jeong Min Park; Dong-Won Woo; Je Hyeong Park; Sang Gab Kim; Jung-Soo Lee; Ji-Hyun Kim
- Web page: https://patentgrep.com/patent/US9006742B2

## CPC

- H10D 30/67: Thin-film transistors [TFT] {(Stacked nanowire, nanosheet or nanoribbon FETs H10D30/501)}
- H10D 30/6733: {Multi-gate TFTs}
- H10D 30/674: {characterised by the active materials}
- H10D 86/021: {of multiple TFTs}
- H10D 86/441: {Interconnections, e.g. scanning lines}
- H10D 86/60: wherein the TFTs are in active matrices
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A manufacturing method of a thin film transistor array panel includes: simultaneously forming a gate conductor and a first electrode on a substrate, using a non-peroxide-based etchant; forming a gate insulating layer on the gate conductor and the first electrode; forming a semiconductor, a source electrode, and a drain electrode on the gate insulating layer; forming a passivation layer on the semiconductor, the source electrode, and the drain electrode; and forming a second electrode layer on the passivation layer.

## Claims

### Claim 1

A thin film transistor array panel comprising:
a substrate;
a gate conductor comprising a lower layer disposed on the substrate and an upper layer disposed on the lower layer;
a first electrode disposed on the substrate;
a gate insulating layer disposed on the gate conductor and the first electrode;
a semiconductor disposed on the gate insulating layer;
a source electrode and a drain electrode disposed on the semiconductor;
a passivation layer disposed on the source electrode and the drain electrode; and
a second electrode disposed on the passivation layer,
wherein, the lower layer of the gate conductor and the first electrode are disposed directly on the same layer and comprise the same type of material, and
wherein the lower layer of the gate conductor and the first electrode comprise indium tin oxide (ITO) or indium zinc oxide (IZO), and
wherein the upper layer of the gate conductor comprises copper or a copper alloy.

### Claim 2 (depends on 1)

The thin film transistor array panel of claim 1, wherein the first electrode is a reference electrode and the second electrode is a pixel electrode.

### Claim 3 (depends on 1)

The thin film transistor array panel of claim 1, wherein:
the first electrode covers a pixel area of a substrate; and
the first electrode comprises two or more connections that extend from the first electrode to a first electrode of an adjacent pixel area.

### Claim 4 (depends on 1)

The thin film transistor array panel of claim 1, wherein the first electrode covers substantially all of a pixel area of a substrate.

### Claim 5

A thin film transistor array panel comprising:
a substrate;
a gate conductor comprising a lower layer disposed on the substrate and an upper layer disposed on the lower layer;
a pixel electrode disposed on the substrate;
a gate insulating layer disposed on the gate conductor and the pixel electrode;
a semiconductor disposed on the gate insulating layer;
a source electrode and a drain electrode disposed on the semiconductor;
a passivation layer disposed on the source electrode and the drain electrode; and
a reference electrode disposed on the passivation layer,
wherein, the lower layer of the gate conductor and the pixel electrode are disposed directly on the same layer and comprise the same type of material.

### Claim 6 (depends on 5)

The thin film transistor array panel of claim 5, wherein the upper layer of the gate conductor comprises copper or a copper alloy.

### Claim 7 (depends on 6)

The thin film transistor array panel of claim 6, wherein the lower layer of the gate conductor and the pixel electrode comprise indium tin oxide (ITO) or indium.