# US 9,006,104 B2 · Methods of forming metal silicide regions on semiconductor devices using millisecond annealing techniques

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- Number: US 9,006,104 B2
- Document ID: US9006104B2
- Status: Granted
- Kind: B2
- Application number: 13/910,430
- Filed: 2013-06-05
- Published: 2014-12-11
- Granted: 2015-04-14
- Earliest claimed: 2013-06-05
- Assignees: Globalfoundries Inc.
- Applicants: GLOBALFOUNDRIES Inc.
- Inventors: Vidmantas Sargunas
- Web page: https://patentgrep.com/patent/US9006104B2

## CPC

- H10D 64/0112: {using conductive layers comprising silicides}
- H10D 64/01125: {the silicides being formed by chemical reaction with the semiconductor after the contact hole formation}
- H10P 30/204: {into Group IV semiconductors}
- H10P 30/208: {of electrically inactive species}
- H10P 30/226: {at a temperature lower than room temperature}
- H10W 20/033: {in openings in dielectrics}
- H10W 20/047: {by introducing additional elements therein}
- H10D 30/0212: {using self-aligned silicidation}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

In one example, the method includes forming a metal layer on a silicon-containing structure, after forming the metal layer, performing an ion implantation process to implant silicon atoms into at least one of the metal layer and the silicon-containing structure and performing a first millisecond anneal process so as to form a first metal silicide region in the silicon-containing structure.

## Claims

### Claim 1

A method, comprising:
forming a metal layer on a silicon-containing structure;
after forming said metal layer, performing an ion implantation process to implant silicon atoms into at least one of said metal layer and said silicon-containing structure;
performing a first millisecond anneal process at a temperature that falls within the range of 400-700° C. for a duration of less than one millisecond so as to form a first metal silicide region in said silicon-containing structure; and
performing a second millisecond anneal process on said first metal silicide for a duration of less than one millisecond.

### Claim 2 (depends on 1)

The method of claim 1, further comprising, after forming said first metal silicide region and prior to performing said second millisecond anneal process, stripping portions of said metal layer.

### Claim 3 (depends on 2)

The method of claim 2, wherein said second millisecond anneal process is performed at a temperature that falls within the range of 600-850° C. so as to convert said first metal silicide region into a second metal silicide region that has a lower resistance than that of said first metal silicide region.

### Claim 4 (depends on 1)

The method of claim 1, wherein performing said ion implantation process comprises performing said ion implantation process at a temperature that is less than or equal to −50° C.

### Claim 5 (depends on 1)

The method of claim 1, wherein performing said ion implantation process comprises performing said ion implantation process at a temperature that falls within the range of −50 to −100° C.

### Claim 6 (depends on 1)

The method of claim 1, wherein performing said ion implantation process comprises performing said ion implantation process using a dopant dose that falls within the range of 3-5 e15 atoms/cm2.

### Claim 7 (depends on 6)

The method of claim 6, wherein performing said ion implantation process comprises performing said ion implantation process using an energy level that falls within the range of 15-50 keV.

### Claim 8 (depends on 1)

The method of claim 1, wherein said metal layer is comprised of a refractory metal.

### Claim 9 (depends on 1)

The method of claim 1, wherein said metal layer is comprised of nickel, cobalt, titanium, platinum or a combination of such materials.

### Claim 10 (depends on 1)

The method of claim 1, wherein said silicon-containing structure is comprised of one of crystalline silicon, polysilicon, germanium or silicon-germanium.

### Claim 11 (depends on 1)

The method of claim 1, wherein said silicon-containing structure is a doped source/drain region of a transistor device.

### Claim 12

A method, comprising:
forming a metal layer on a silicon-containing structure;
after forming said metal layer, performing an ion implantation process to implant silicon atoms into at least one of said metal layer and said silicon-containing structure, wherein said ion implantation process is performed at a temperature less than or equal to −50° C.;
performing a first millisecond anneal process for a duration of less than one millisecond so as to form a first metal silicide region in said silicon-containing structure;
after forming said first metal silicide region, stripping portions of said metal layer; and
performing a second millisecond anneal process for a duration of less than one millisecond so as to convert said first metal silicide region into a second metal silicide region that has a lower resistance than that of said first metal silicide region.

### Claim 13 (depends on 12)

The method of claim 12, wherein said first millisecond anneal process is performed at a temperature that falls within the range of 400-700° C.

### Claim 14 (depends on 13)

The method of claim 13, wherein said second millisecond anneal process is performed at a temperature that falls within the range of 600-850° C.

### Claim 15 (depends on 12)

The method of claim 12, wherein said ion implantation process is performed at a temperature that falls within the range of −50 to −100° C.

### Claim 16 (depends on 12)

The method of claim 12, wherein performing said ion implantation process comprises performing said ion implantation process using a dopant dose that falls within the range of 3-5 e15 atoms/cm2.

### Claim 17 (depends on 16)

The method of claim 16, wherein performing said ion implantation process comprises performing said ion implantation process using an energy level that falls within the range of 15-50 keV.

### Claim 18

A method, comprising:
forming a metal layer on a silicon-containing structure;
after forming said metal layer, performing an ion implantation process to implant silicon atoms into at least one of said metal layer and said silicon-containing structure, wherein said ion implantation process is performed at a temperature that falls within the range of −50 to −100° C. using a dopant dose that falls within the range of 3-5 e15 atoms/cm2;
performing a first millisecond anneal process at a temperature that falls within the range of 400-700° C. for a duration of less than one millisecond so as to form a first metal silicide region in said silicon-containing structure;
after forming said first metal silicide region, stripping portions of said metal layer; and
performing a second millisecond anneal process at a temperature that falls within the range of 600-850° C. for a duration of less than one millisecond so as to convert said first metal silicide region into a second metal silicide region that has a lower resistance than that of said first metal silicide region.

### Claim 19 (depends on 18)

The method of claim 18, wherein performing said ion implantation process comprises performing said ion implantation process using an energy level that falls within the range of 15-50 keV.

### Claim 20 (depends on 18)

The method of claim 18, wherein said metal layer is comprised of a refractory metal.

### Claim 21 (depends on 1)

The method of claim 1, wherein said second millisecond anneal process is performed at a temperature that falls within the range of 600-850° C.

### Claim 22 (depends on 1)

The method of claim 1, wherein said first metal silicide region is converted into a second metal silicide region that has a lower resistance than that of said first metal silicide region during said second millisecond anneal process.