# US 9,006,022 B2 · Method for fabricating phase change memory

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- Number: US 9,006,022 B2
- Document ID: US9006022B2
- Status: Granted
- Kind: B2
- Application number: 14/056,253
- Filed: 2013-10-17
- Published: 2014-06-05
- Granted: 2015-04-14
- Earliest claimed: 2012-12-04
- Assignees: Semiconductor Manufacturing International (Shanghai) Corporation
- Applicants: Semiconductor Manufacturing International (Shanghai) Corporation
- Inventors: Ying Li; Neil Zhu; Guanping Wu
- Web page: https://patentgrep.com/patent/US9006022B2

## CPC

- H10N 70/231: {based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect}
- H10N 70/066: {by filling of openings, e.g. damascene method}
- H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices}
- H10N 70/8265: {on sidewalls of dielectric structures, e.g. mesa-shaped or cup-shaped devices}
- H10N 70/841: {Electrodes}
- H10N 70/8828: {Tellurides, e.g. GeSbTe}
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

A method is provided for fabricating a phase change memory. The method includes providing a semiconductor substrate having a bottom electrode connecting with one or more semiconductor devices, and forming a first dielectric layer on the semiconductor substrate. The method also includes forming a loop-shape electrode in the first dielectric layer, and forming a second dielectric layer having a first opening exposing a portion of the first dielectric layer and a portion of the loop-shape electrode. Further, the method includes forming a phase change layer in the first opening of the second dielectric layer such that a contact area between the phase change layer and the loop-shape electrode may be controlled to achieve desired contact, and forming a top electrode.

## Claims

### Claim 1

A method for fabricating a phase change memory, comprising:
providing a semiconductor substrate having a bottom electrode connecting with one or more semiconductor devices;
forming a first dielectric layer on the semiconductor substrate;
forming a loop-shape electrode in the first dielectric layer;
forming a second dielectric layer having a first opening exposing a portion of the first dielectric layer and a portion of the loop-shape electrode;
forming a phase change layer in the first opening of the second dielectric layer such that a contact area between the phase change layer and the loop-shape electrode may be controlled to achieve desired contact; and
forming a top electrode, wherein forming the first dielectric layer and the loop-shape electrode further includes:
forming a fifth dielectric layer on the semiconductor substrate;
forming a third opening in the fifth dielectric layer;
forming a loop-shape electrode material layer in the third opening covering bottom and sidewall of the third opening;
forming a sixth dielectric layer on the loop-shape electrode material layer; and
polishing the sixth dielectric layer and the loop-shape electrode material layer until the fifth dielectric layer is exposed, such that the loop-shape electrode material layer forms the loop-shape electrode, and the fifth dielectric layer and the sixth dielectric layer form the first dielectric layer.

### Claim 2 (depends on 1)

The method according to claim 1, wherein before forming the second dielectric layer, further including:
forming an isolation structure covering a portion of the loop-shape electrode.

### Claim 3 (depends on 2)

The method according to claim 2, wherein forming the second dielectric layer and the phase change layer further includes:
forming a seventh dielectric layer covering the fifth dielectric layer, a portion of the sixth dielectric layer and portion of the isolation structure, wherein the second dielectric layer includes the seventh dielectric layer;
forming the first opening in the seventh dielectric layer; and
forming the phase change material layer.

### Claim 4 (depends on 1)

The method according to claim 1, wherein after forming the phase change layer, further including:
forming a contact metal layer;
forming a third dielectric layer;
polishing the third dielectric layer and the contact metal layer until the second dielectric layer is exposed;
forming a fourth dielectric layer covering the third dielectric layer, the contact metal layer and the phase change layer;
forming a second opening in the fourth dielectric layer to expose a portion of the phase change layer; and
forming a top electrode material layer in the second open to electrically connect with the contact metal layer.

### Claim 5 (depends on 1)

The method according to claim 1, wherein:
the phase change layer is formed by a chemical vapor deposition process or a physical vapor deposition process.

### Claim 6 (depends on 1)

The method according to claim 1, wherein:
the phase change layer is made of GeiSbjTek, or nitrogen, oxygen or carbon doped GeiSbjTek;
wherein:
i, j and k real are numbers referring to atomic percentages;
0≦i<1;
0≦j<1;
0≦k<1; and
i+j+k=1.

### Claim 7 (depends on 1)

The method according to claim 1, wherein:
from a top view, the loop-shape electrode is rectangular.

### Claim 8

A method for fabricating a phase change memory, comprising:
providing a semiconductor substrate having a bottom electrode connecting with one or more semiconductor devices;
forming a first dielectric layer on the semiconductor substrate;
forming a loop-shape electrode in the first dielectric layer;
forming a second dielectric layer having a first opening exposing a portion of the first dielectric layer and a portion of the loop-shape electrode, wherein the second dielectric layer is a stacked layer made of silicon oxide and silicon nitride, and the silicon oxide is on top of the silicon nitride;
forming a phase change layer in the first opening of the second dielectric layer such that a contact area between the phase change layer and the loop-shape electrode may be controlled to achieve desired contact; and
forming a top electrode.

### Claim 9 (depends on 8)

The method according to claim 8, wherein before forming the second dielectric layer, further including:
forming an isolation structure covering a portion of the loop-shape electrode.

### Claim 10 (depends on 9)

The method according to claim 9, wherein forming the second dielectric layer and the phase change layer further includes:
forming a seventh dielectric layer covering the first dielectric layer and portion of the isolation structure, wherein the second dielectric layer includes the seventh dielectric layer;
forming the first opening in the seventh dielectric layer; and
forming the phase change material layer.

### Claim 11 (depends on 8)

The method according to claim 8, wherein after forming the phase change layer, further including:
forming a contact metal layer;
forming a third dielectric layer;
polishing the third dielectric layer and the contact metal layer until the second dielectric layer is exposed;
forming a fourth dielectric layer covering the third dielectric layer, the contact metal layer and the phase change layer;
forming a second opening in the fourth dielectric layer to expose a portion of the phase change layer; and
forming a top electrode material layer in the second open to electrically connect with the contact metal layer.

### Claim 12 (depends on 8)

The method according to claim 8, wherein:
the phase change layer is formed by a chemical vapor deposition process or a physical vapor deposition process.

### Claim 13 (depends on 8)

The method according to claim 8, wherein:
the phase change layer is made of GeiSbjTek, or nitrogen, oxygen or carbon doped GeiSbjTek;
wherein:
j and k real are numbers referring to atomic percentages;
0≦i<1;
0≦j<1;
0≦k<1; and
i+j+k=1.

### Claim 14 (depends on 8)

The method according to claim 8, wherein:
from a top view, the loop-shape electrode is rectangular.

### Claim 15

A method for fabricating a phase change memory, comprising:
providing a semiconductor substrate having a bottom electrode connecting with one or more semiconductor devices;
forming a first dielectric layer on the semiconductor substrate;
forming a loop-shape electrode in the first dielectric layer;
forming a second dielectric layer having a first opening exposing a portion of the first dielectric layer and a portion of the loop-shape electrode;
forming a transitional layer;
forming a phase change layer in the first opening of the second dielectric layer such that a contact area between the phase change layer and the loop-shape electrode may be controlled to achieve desired contact, the transitional layer being between the phase change layer and the loop-shape electrode; and
forming a top electrode.

### Claim 16 (depends on 15)

The method according to claim 15, wherein before forming the second dielectric layer, further including:
forming an isolation structure covering a portion of the loop-shape electrode.

### Claim 17 (depends on 16)

The method according to claim 16, wherein forming the second dielectric layer and the phase change layer further includes:
forming a seventh dielectric layer covering the first dielectric layer and portion of the isolation structure, wherein the second dielectric layer includes the seventh dielectric layer;
forming the first opening in the seventh dielectric layer; and
forming the phase change material layer.

### Claim 18 (depends on 15)

The method according to claim 15, wherein after forming the phase change layer, further including:
forming a contact metal layer;
forming a third dielectric layer;
polishing the third dielectric layer and the contact metal layer until the second dielectric layer is exposed;
forming a fourth dielectric layer covering the third dielectric layer, the contact metal layer and the phase change layer;
forming a second opening in the fourth dielectric layer to expose a portion of the phase change layer; and
forming a top electrode material layer in the second open to electrically connect with the contact metal layer.

### Claim 19 (depends on 15)

The method according to claim 15, wherein:
the phase change layer is formed by a chemical vapor deposition process or a physical vapor deposition process.

### Claim 20 (depends on 15)

The method according to claim 15, wherein:
the phase change layer is made of GeiSbjTek, or nitrogen, oxygen or carbon doped GeiSbjTek;
wherein:
j and k real are numbers referring to atomic percentages;
0≦i<1;
0≦j<1;
0≦k<1; and
i+j+k=1.