System and method for reducing power consumption of integrated circuit
AssigneeFreescale Semiconductor, Inc.
InventorsChetan Verma, Kushagra Khorwal, Amit Roy, Rounak Roy, Vijay Tayal
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Abstract
A method and system for reducing power consumption of an integrated circuit with an EDA tool by analyzing and modifying a layout design having a plurality of nets across multiple metal layers. The method includes identifying long nets in the layout design, determining an interconnect capacitance of each of the long nets, determining a net level switching activity of each of the long nets, generating a high power impact list using the interconnect capacitance and the switching activity of each of the long nets, modifying a metal spacing of the long nets listed in the high power impact list.
Claims14
An electronic design automation (EDA) tool for reducing power consumption of a layout design of an integrated circuit, wherein the layout design includes a plurality of nets across multiple metal layers, the EDA tool comprising:
- a memory used to store the layout design of the integrated circuit;
- and
- a processor, in communication with the memory, wherein the processor includes:
- a long net identifier for identifying long nets in the layout design;
- an interconnect capacitance determining unit for determining an interconnect capacitance of each of the long nets;
- a net level switching activity determining unit for determining a net level switching activity of each of the long nets;
- a high power impact list generator for generating a high power impact list using the interconnect capacitance and the net level switching activity of each of the long nets, wherein the high power impact list generator calculates a product of the interconnect capacitance and the switching activity of each of the long nets, and wherein the high power impact list lists the long nets in a descending order of the product such that the long nets are modified in the descending order of the product;
- a pre-router for pre-routing the long nets listed in the high power impact list prior to routing any other nets in the layout design, and wherein the number of the long nets to be modified is based on routability of the layout design;
- and
- a metal spacing modifier for modifying a metal spacing of the long nets listed in the high power impact list from adjacent nets.
A method for reducing power consumption of an integrated circuit with an Electronic Design Automation (EDA) tool by analyzing and modifying a layout design of the integrated circuit, wherein the layout design includes a plurality of nets across multiple metal layers, wherein the EDA tool includes a memory for storing the layout design and a processor coupled to the memory, wherein the method comprises the processor performing the following steps:
- identifying long nets in the layout design;
- determining an interconnect capacitance of each of the long nets;
- determining a net level switching activity of each of the long nets;
- generating a high power impact list using the interconnect capacitance and the switching activity of each of the long nets, wherein generating the high power impact list includes calculating a product of the interconnect capacitance and the switching activity of each of the long nets, and wherein generating the high power impact list includes listing the long nets in a descending order of the product, such that the long nets in the high power impact list are modified in the descending order of the product;
- pre-routing the long nets listed in the high power impact list prior to routing any other nets in the layout design, and wherein the number of the long nets to be modified is based on routability of the layout design;
- modifying a metal spacing of the long nets listed in the high power impact list from adjacent nets;
- and
- generating and storing an updated layout design that includes the modified metal spacing of the long nets listed in the high power impact list in the memory.
Dependencies are inferred from the claim text.