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AssigneeCypress Semiconductor Corporation
InventorsAvijit Dutta, Krishnan Anandh, Steven Danz, Neil Tuttle, Ryan Morse, Haneef Mohammed
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Techniques for reducing post-routing delay variance are described herein. In an example embodiment, an initial netlist includes multiple instances that represent digital components of an electronic design. An base signature is assigned to each instance in the initial netlist, where the base signature is based on two or more design or connectivity attributes of the instance. The base signatures are then used to generate an initial instance ordering of the instances in the initial netlist. A subsequent netlist, different from the initial netlist but representing the same electronic design, is received. Base signatures are assigned to the instances on the subsequent netlist and a subsequent instance ordering is generated. The subsequent instance ordering preserves the same order as the initial instance ordering for those instances that are included in both the initial netlist and the subsequent netlist. In this manner, any later netlist-based processing (e.g., such as packing, placement, and routing) is shielded from the negative re-design effects caused by the subsequent changes to the initial netlist and, consequently, the post-routing timing delay variance of the electronic design is reduced.
A method for reducing post-routing delay variance, the method comprising:
A non-transitory computer-readable medium storing a set of instructions that comprise instructions which, when executed by one or more processors, cause the one or more processors to perform steps comprising:
Dependencies are inferred from the claim text.